Inventor
William Jeffrey Schaefer
Inventor
San Jose, CA, US
Overview
Patents· 8 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1067%
H05KPrinted circuits17%
Y10TTechnical subjects covered by former us classification17%
PatentTitleYear
7,287,323'Materials and structure for a high reliability BGA connection between LTCC and PB boards'2007RE038789'Semiconductor wafer having a bottom surface protective coating'20056,800,815'Materials and structure for a high reliability bga connection between LTCC and PB boards'20046,770,513'Thermally enhanced flip chip packaging arrangement'20046,175,162'Semiconductor wafer having a bottom surface protective coating'20016,084,308'Chip-on-chip integrated circuit package and method for making the same'20006,075,290'Surface mount die: wafer level chip-scale package and process for making the same'20006,023,094'Semiconductor wafer having a bottom surface protective coating'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2007Patents assigned to NAT SEMICONDUCTOR CORP (8)· patent assignee history
2000–2007Based in San Jose, CA, US· patent location history
2005Based in Dublin, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NAT SEMICONDUCTOR CORP | 8 | 2000–2007 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 7 | 2000–2007 |
| Dublin, California, US | 1 | 2005 |