Inventor

Saroj Pathak

Inventor
Los Altos Hills, CA, US

Overview

25→
Patents
1980–2021
Patent span
Physics
Primary field (CPC G)

Patents· 25 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores45%
H03KPulse technique18%
G05FSystems for regulating electric or magnetic variables5%
G09GArrangements or circuits for control of indicating devices using static means to present variable information5%
B25JManipulators3%
G01RMeasuring electric variables3%
G06FElectric digital data processing3%
G06NComputing arrangements based on specific computational models3%
H01HElectric switches3%
H02HEmergency protective circuit arrangements3%
PatentTitleYear
10,940,587Data association aware belief space planning and perception20216,809,550'High speed zero DC power programmable logic device (PLD) architecture'20046,618,289'High voltage bit/column latch for Vcc operation'20036,476,785'Drive circuit for liquid crystal display cell'20026,411,549'Reference cell for high speed sensing in non-volatile memories'20026,320,454'Low power voltage regulator circuit for use in an integrated circuit device'20016,140,993'Circuit for transferring high voltage video signal without signal loss'20006,115,305'Method and apparatus for testing a video display chip'20005,999,038'Fuse circuit having zero power draw for partially blown condition'19995,963,496'Sense amplifier with zero power idle mode'19995,946,267'Zero power high speed configuration memory'19995,936,444'Zero power power-on reset circuit'19995,917,754'Semiconductor memory having a current balancing circuit'19995,781,469'Bitline load and precharge structure for an SRAM memory'19985,731,734'Zero power fuse circuit'19985,680,346'High-speed, non-volatile electrically programmable and erasable cell and method'19975,493,244'Breakdown protection circuit using high voltage detection'19965,473,500'Electrostatic discharge circuit for high speed, high voltage circuitry'19955,440,508'Zero power high speed programmable circuit device architecture'19955,383,193'Method for testing non-volatile memories'19955,272,674'High speed memory sense amplifier with noise reduction'19935,027,320'EPROM circuit having enhanced programmability and improved speed and reliability'19914,978,905'Noise reduction output buffer'19904,264,828'MOS Static decoding circuit'19814,223,394'Sensing amplifier for floating gate memory devices'1980

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1980–1981Patents assigned to INTEL CORP (2)· patent assignee history
1980–1981Based in Campbell, CA, US· patent location history
1990–1991Patents assigned to CYPRESS SEMICONDUCTOR CORP (2)· patent assignee history
1990–2004Based in Los Altos Hills, CA, US· patent location history
1993–2004Patents assigned to ATMEL CORP (20)· patent assignee history
2021Patents assigned to TECHNION RES & DEV FOUNDATION (1)· patent assignee history
2021Based in Allahabad, IN· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ATMEL CORP201993–2004
CYPRESS SEMICONDUCTOR CORP21990–1991
INTEL CORP21980–1981
TECHNION RES & DEV FOUNDATION12021
Locations
LocationPatentsSpan
Los Altos Hills, California, US221990–2004
Campbell, California, US21980–1981
Allahabad, IN12021