Inventor
Jarvis Benjamin Jacobs
Inventor
Murphy, TX, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices35%
H01LSemiconductor devices25%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices4%
G03BApparatus or arrangements for taking photographs or for projecting or viewing them2%
PatentTitleYear
10,714,474High voltage CMOS with triple gate oxide202010,566,200Method of fabricating transistors, including ambient oxidizing after etchings into barrier layers and anti-reflecting coatings20209,865,691'Poly sandwich for deep trench fill'20189,741,718'High voltage CMOS with triple gate oxide'20179,583,579'Poly sandwich for deep trench fill'20179,431,286'Deep trench with self-aligned sinker'20169,401,410'Poly sandwich for deep trench fill'20169,117,687'High voltage CMOS with triple gate oxide'20159,054,056'Transistor performance using a two-step damage anneal'20159,029,251'Transistor performance using a two-step damage anneal'20158,828,855'Transistor performance using a two-step damage anneal'20148,802,577'Method for manufacturing a semiconductor device using a nitrogen containing oxide layer'20147,569,464'Method for manufacturing a semiconductor device having improved across chip implant uniformity'20097,562,333'Method and process for generating an optical proximity correction model based on layout density'20097,560,779'Method for forming a mixed voltage circuit having complementary devices'20096,866,974'Semiconductor process using delay-compensated exposure'20056,762,130'Method of photolithographically forming extremely narrow transistor gate elements'20046,583,013'Method for forming a mixed voltage circuit having complementary devices'20035,936,278'Semiconductor on silicon (SOI) transistor with a halo implant'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2020Patents assigned to TEXAS INSTRUMENTS INC (19)· patent assignee history
1999Based in Dallas, TX, US· patent location history
2003–2009Based in Richardson, TX, US· patent location history
2004–2020Based in Murphy, TX, US· patent location history
2014Patents assigned to NIIMI HIROAKI (2)· patent assignee history
2014Patents assigned to JACOBS JARVIS B (1)· patent assignee history
2014Patents assigned to JACOBS JARVIS BENJAMIN (1)· patent assignee history
2014Patents assigned to LAAKSONEN REIMA TAPANI (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 19 | 1999–2020 |
| NIIMI HIROAKI | 2 | 2014 |
| JACOBS JARVIS Bself | 1 | 2014 |
| JACOBS JARVIS BENJAMINself | 1 | 2014 |
| LAAKSONEN REIMA TAPANI | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Murphy, Texas, US | 16 | 2004–2020 |
| Richardson, Texas, US | 2 | 2003–2009 |
| Dallas, Texas, US | 1 | 1999 |