Inventor

Chau-Chad Tsai

Inventor

Taipei, TW

Overview

18→

Patents

2003–2011

Patent span

Physics

Primary field (CPC G)

Patents· 18 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing85%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use10%

H04LTransmission of digital information, e.g. telegraphic communication5%

PatentTitleYear

8,060,676'Method of hot switching data transfer rate on bus'2011 7,805,567'Chipset and northbridge with raid access'2010 7,136,955'Expansion adapter supporting both PCI and AGP device functions'2006 7,107,373'Method of hot switching data transfer rate on bus'2006 7,051,148'Data transmission sequencing method associated with briding device and application system'2006 6,941,398'Processing method, chip set and controller for supporting message signaled interrupt'2005 6,934,789'Interface, structure and method for transmitting data of PCI bus which uses bus request signal for judging whether a device supporting dual transmission mode'2005 6,925,517'Bus for supporting plural signal line configurations and switch method thereof'2005 6,836,829'Peripheral device interface chip cache and data synchronization method'2004 6,795,883'Method and system for dividing configuration space'2004 6,721,833'Arbitration of control chipsets in bus transaction'2004 6,718,400'Data accessing system with an access request pipeline and access method thereof'2004 6,694,400'PCI system controller capable of delayed transaction'2004 6,684,284'Control chipset, and data transaction method and signal transmission devices therefor'2004 6,678,771'Method of adjusting an access sequencing scheme for a number of PCI- compliant units coupled to a PCI bus system'2004 6,622,213'Two-way cache system and method for interfacing a memory unit with a peripheral device using first and second cache data regions'2003 6,549,964'Delayed transaction method and device used in a PCI system'2003 6,546,448'Method and apparatus for arbitrating access to a PCI bus by a plurality of functions in a multi-function master'2003

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2003–2011Patents assigned to VIA TECH INC (18)· patent assignee history

2003–2010Based in Taipei, TW· patent location history

2011Patents assigned to KAO CHIH-KUO (1)· patent assignee history

2011Patents assigned to TSAI CHAU-CHAD (1)· patent assignee history

2011Patents assigned to TSAI CHI-CHE (1)· patent assignee history

2011Based in Hsin-Tien, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
VIA TECH INC	18	2003–2011
KAO CHIH-KUO	1	2011
TSAI CHAU-CHADself	1	2011
TSAI CHI-CHE	1	2011

Locations

Location	Patents	Span
Taipei, TW	17	2003–2010
Hsin-Tien, TW	1	2011