Inventor
Mamun Ur Rashid
Inventor
Folsom, CA, US
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing33%
G11CStatic stores28%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses15%
G01RMeasuring electric variables8%
H04LTransmission of digital information, e.g. telegraphic communication8%
H03KPulse technique5%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
PatentTitleYear
8,225,016'Even and odd frame combination data path architecture'20127,954,001'Nibble de-skew method, apparatus, and system'20117,805,627'Clock synchronization scheme for deskewing operations in a data interface'20107,684,267'Method and apparatus for memory redundancy in a microprocessor'20107,668,524'Clock deskewing method, apparatus, and system'20107,590,789'Optimizing clock crossing and data path latency'20097,555,670'Clocking architecture using a bidirectional clock port'20097,439,788'Receive clock deskewing method, apparatus, and system'20087,401,246'Nibble de-skew method, apparatus, and system'20087,388,795'Modular memory controller clocking architecture'20087,324,403'Latency normalization by balancing early and late clocks'20087,230,464'Closed-loop delay compensation for driver'20077,109,768'Closed-loop control of driver slew rate'20067,061,224'Test circuit for delay lock loops'20066,958,634'Programmable direct interpolating delay locked loop'20055,835,927'Special test modes for a page buffer shared resource in a memory device'19985,822,256'Method and circuitry for usage of partially functional nonvolatile memory'19985,802,552'System and method for allocating and sharingpage buffers for a flash memory device'19985,623,620'Special test modes for a page buffer shared resource in a memory device'19975,586,081'Synchronous address latching for memory arrays'19965,523,972'Method and apparatus for verifying the programming of multi-level flash EEPROM memory'19965,497,355'Synchronous address latching for memory arrays'19965,410,544'External tester control for flash memory'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2012Patents assigned to INTEL CORP (22)· patent assignee history
1995–1998Based in Fairfield, CA, US· patent location history
1996Based in Davis, CA, US· patent location history
2005–2012Based in Folsom, CA, US· patent location history
2010Patents assigned to SUN MICROSYSTEMS INC (1)· patent assignee history
2010Based in Pleasanton, CA, US· patent location history
2012Patents assigned to RASHID MAMUN UR (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 22 | 1995–2012 |
| RASHID MAMUN URself | 1 | 2012 |
| SUN MICROSYSTEMS INC | 1 | 2010 |
Locations
| Location | Patents | Span |
|---|---|---|
| Folsom, California, US | 14 | 2005–2012 |
| Fairfield, California, US | 7 | 1995–1998 |
| Pleasanton, California, US | 1 | 2010 |
| Davis, California, US | 1 | 1996 |