Inventor
Guoxiang Ning
Inventor
Clifton Park, NY, US
Overview
Patents· 37 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G03Fprimary
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices23%
H01LSemiconductor devices19%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%
G06FElectric digital data processing11%
H10DInorganic electric semiconductor devices9%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%
Y02PClimate change mitigation technologies in the production or processing of goods4%
G01RMeasuring electric variables2%
C23CCoating metallic material1%
G01NInvestigating or analysing materials by determining their chemical or physical properties1%
PatentTitleYear
11,037,937SRAM bit cells formed with dummy structures202110,816,483Double pass diluted ultraviolet reticle inspection202010,804,170Device/health of line (HOL) aware eBeam based overlay (EBO OVL) structure202010,777,413Interconnects with non-mandrel cuts formed by early block patterning202010,770,344Chamferless interconnect vias of semiconductor devices202010,727,120Controlling back-end-of-line dimensions of semiconductor devices202010,714,422Anti-fuse with self aligned via patterning202010,642,160Self-aligned quadruple patterning pitch walking solution202010,627,720Overlay mark structures202010,483,214Overlay structures201910,423,078FinFET cut isolation opening revision to compensate for overlay inaccuracy201910,386,726Geometry vectorization for mask process correction201910,332,745Dummy assist features for pattern support201910,324,381FinFET cut isolation opening revision to compensate for overlay inaccuracy201910,199,271Self-aligned metal wire on contact structure and method for forming same201910,002,827Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an IC device20189,864,831'Metrology pattern layout and method of use thereof'20189,817,940'Method wherein test cells and dummy cells are included into a layout of an integrated circuit'20179,791,772'Monitoring pattern for devices'20179,672,312'Method wherein test cells and dummy cells are included into a layout of an integrated circuit'20179,672,313'Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an IC device'20179,658,531'Semiconductor device resolution enhancement by etching multiple sides of a mask'20179,645,486'Multiple threshold convergent OPC model'20179,606,432'Alternating space decomposition in circuit structure fabrication'20179,535,319'Reticle, system comprising a plurality of reticles and method for the formation thereof'20179,500,945'Pattern classification based proximity corrections for reticle fabrication'20169,384,318'Mask error compensation by optical modeling calibration'20169,368,453'Overlay mark dependent dummy fill to mitigate gate height variation'20169,329,471'Achieving a critical dimension target based on resist characteristics'20169,323,882'Metrology pattern layout and method of use thereof'20169,252,061'Overlay mark dependent dummy fill to mitigate gate height variation'20169,250,538'Efficient optical proximity correction repair flow method and apparatus'20169,236,301'Customized alleviation of stresses generated by through-substrate via(S)'20169,136,223'Forming alignment mark and resulting mark'20158,907,496'Circuit structures and methods of fabrication with enhanced contact via electrical connection'20148,895,211'Semiconductor device resolution enhancement by etching multiple sides of a mask'20147,923,180'Cross technology reticles'2011Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2011Patents assigned to CHARTERED SEMICONDUCTOR MFG (1)· patent assignee history
2011Based in Singapore, SG· patent location history
2014–2020Patents assigned to GLOBALFOUNDRIES INC (33)· patent assignee history
2014–2021Based in Clifton Park, NY, US· patent location history
2015–2019Based in Ballston Lake, NY, US· patent location history
2016–2017Patents assigned to GLOBALFOUNDRIES SG PTE LTD (2)· patent assignee history
2021Patents assigned to GLOBALFOUNDRIES US INC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| GLOBALFOUNDRIES INC | 33 | 2014–2020 |
| GLOBALFOUNDRIES SG PTE LTD | 2 | 2016–2017 |
| CHARTERED SEMICONDUCTOR MFG | 1 | 2011 |
| GLOBALFOUNDRIES US INC | 1 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Clifton Park, New York, US | 20 | 2014–2021 |
| Ballston Lake, New York, US | 16 | 2015–2019 |
| Singapore, SG | 1 | 2011 |