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Inventor

Oscar M. Siguenza

Inventor
San Jose, CA, US

Overview

5→
Patents
2001–2017
Patent span
Electricity
Primary field (CPC H)

Patents· 5 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary
H03KPulse technique44%
G06FElectric digital data processing22%
H02JElectric power networks11%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications11%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use11%
PatentTitleYear
9,614,386'Method and apparatus for power switching'20179,559,672'Ser tolerant flip flop having a redundant latch'20178,427,216'Ser tolerant flip flop having a redundant latch'20138,392,862'Structures and methods for optimizing power consumption in an integrated chip design'20136,184,711'Low impact signal buffering in integrated circuits'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001Patents assigned to LSI LOGIC CORP (1)· patent assignee history
2001–2017Based in San Jose, CA, US· patent location history
2013–2017Patents assigned to MARVELL INT LTD (2)· patent assignee history
2013Patents assigned to BREID DUANE (1)· patent assignee history
2013Patents assigned to CHITTURI VINAY (1)· patent assignee history
2013Patents assigned to COLWELL MIKE (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MARVELL INT LTD22013–2017
BREID DUANE12013
CHITTURI VINAY12013
COLWELL MIKE12013
LSI LOGIC CORP12001
Locations
LocationPatentsSpan
San Jose, California, US52001–2017