Inventor
Satoru Tanoi
Inventor
Tokyo, JP
Overview
Patents· 38 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores40%
G06FElectric digital data processing17%
H03KPulse technique12%
G01RMeasuring electric variables9%
G05FSystems for regulating electric or magnetic variables5%
H03FAmplifiers3%
H04LTransmission of digital information, e.g. telegraphic communication3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
G06GAnalogue computers2%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems2%
PatentTitleYear
10,897,230Bias circuit and amplification apparatus20217,397,309'Bias circuit for a wideband amplifier driven with low voltage'20086,522,563'Semiconductor memory with built-in cache'20036,510,070'Semiconductor memory with built-in cache'20036,362,989'Semiconductor memory with built-in cache'20026,320,778'Semiconductor memory with built-in cache'20016,249,450'Semiconductor memory with built-in cache'20016,195,771'Semiconductor device having semiconductor memory circuit to be tested, method of testing semiconductor memory circuit and read circuit for semiconductor memory circuit'20016,104,655'Semiconductor storage device'20006,011,709'Semiconductor memory with built-in cache'20005,903,488'Semiconductor memory with improved word line structure'19995,875,148'Semiconductor memory'19995,821,777'Current amplifier and data bus circuit'19985,781,466'Semiconductor memory with built-in cache'19985,751,665'Clock distributing circuit'19985,751,177'Variable level shifter and multiplier suitable for low-voltage differential operation'19985,739,719'Bias circuit with low sensitivity to threshold variations'19985,708,621'Semiconductor memory with improved word line structure'19985,659,258'Level shifter circuit'19975,648,734'Buffer circuit and bias circuit'19975,640,117'Digital signal transmission circuit'19975,596,521'Semiconductor memory with built-in cache'19975,592,499'Semiconductor memory device'19975,577,223'Dynamic random access memory (DRAM) with cache and tag'19965,559,462'Digital signal transmission circuit'19965,519,348'Sense circuit, memory circuit, negative-resistance circuit, schmitt trigger, load circuit, level shifter, and amplifier'19965,514,986'Sense circuit, memory circuit, negative-resistance circuit, schmitt trigger, load circuit, level shifter, and amplifier'19965,510,746'Load circuit tolerating large current and voltage swings'19965,511,030'Semiconductor memory device and method of driving same'19965,504,442'Sense circuit'19965,498,991'Level shifter circuit'19965,489,874'Inverting amplifier having negative-resistance circuit'19965,483,204'Clock circuit'19965,430,335'Simplified low-noise output buffer circuit'19955,331,207'Latch circuit with independent propagation delays'19945,237,213'Semiconductor integrated circuit with low-noise output buffers'19934,996,447'Field-effect transistor load circuit'19914,924,440'MOS gate array devices'1990Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1990–2008Patents assigned to OKI ELECTRIC IND CO LTD (37)· patent assignee history
1990–2008Based in Tokyo, JP· patent location history
2021Patents assigned to UNIV TOHOKU (1)· patent assignee history
2021Based in Miyagi, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| OKI ELECTRIC IND CO LTD | 37 | 1990–2008 |
| UNIV TOHOKU | 1 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 37 | 1990–2008 |
| Miyagi, JP | 1 | 2021 |