Inventor
Reza Kazerounian
Inventor
Alameda, CA, US
Overview
Patents· 15 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores38%
H10BElectronic memory devices35%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems8%
H10DInorganic electric semiconductor devices8%
G05FSystems for regulating electric or magnetic variables4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
PatentTitleYear
6,055,203'Row decoder'20005,949,711'Dual bit memory cell'19995,910,016'Scalable EPROM array'19995,732,015'SRAM with a programmable reference voltage'19985,683,925'Manufacturing method for ROM array with minimal band-to-band tunneling'19975,623,443'Scalable EPROM array with thick and thin non-field oxide gate insulators'19975,568,085'Unit for stabilizing voltage on a capacitive node'19965,557,124'Flash EEPROM and EPROM arrays with select transistors within the bit line pitch'19965,327,378'Easily manufacturable compact EPROM'19945,151,375'EPROM virtual ground array'19925,042,009'Method for programming a floating gate memory device'19915,021,847'Split gate memory array having staggered floating gate rows and method for making same'19915,014,097'On-chip high voltage generator and regulator in an integrated circuit'19915,006,974'On-chip high voltage generator and regulator in an integrated circuit'19914,758,869'Nonvolatile floating gate transistor structure'1988Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1988–1999Patents assigned to WAFERSCALE INTEGRATION INC (14)· patent assignee history
1988Based in Fremont, CA, US· patent location history
1991–2000Based in Alameda, CA, US· patent location history
1997Patents assigned to AMERICAN MICRO SYST (1)· patent assignee history
1999Based in Danville, CA, US· patent location history
2000Patents assigned to WAFERSCALE INTEGRATION (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| WAFERSCALE INTEGRATION INC | 14 | 1988–1999 |
| AMERICAN MICRO SYST | 1 | 1997 |
| WAFERSCALE INTEGRATION | 1 | 2000 |
Locations
| Location | Patents | Span |
|---|---|---|
| Alameda, California, US | 13 | 1991–2000 |
| Danville, California, US | 1 | 1999 |
| Fremont, California, US | 1 | 1988 |