Inventor
Avinash Srikrishnan Kashyap
Inventor
Niskayuna, NY, US
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices37%
H01LSemiconductor devices24%
H02HEmergency protective circuit arrangements13%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
G01RMeasuring electric variables4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
Y10TTechnical subjects covered by former us classification4%
H01BCables2%
PatentTitleYear
10,811,494Method and assembly for mitigating short channel effects in silicon carbide MOSFET devices202010,511,163Low capacitance surge suppression device201910,186,509Method and system for a semiconductor device with integrated transient voltage suppression201910,103,540Method and system for transient voltage suppression devices with active control201810,014,388Transient voltage suppression devices with symmetric breakdown characteristics20189,997,507Semiconductor assembly and method of manufacture20189,947,647Method and system for over-voltage protection using transient voltage suppression devices20189,806,157'Structure and method for transient voltage suppression devices with a two-region base'20179,508,841'Method and system for a semiconductor device with integrated transient voltage suppression'20169,130,365'Method and system for ultra miniaturized packages for transient voltage suppressors'20159,111,750'Over-voltage protection of gallium nitride semiconductor devices'20159,042,072'Method and system for lightning protection with distributed transient voltage suppression'20158,987,858'Method and system for transient voltage suppression'20158,835,976'Method and system for ultra miniaturized packages for transient voltage suppressors'20148,765,524'Method and system for transient voltage suppressors'20148,730,629'Variable breakdown transient voltage suppressor'20148,608,376'Method for modeling and parameter extraction of LDMOS devices'20138,530,902'System for transient voltage suppressors'2013Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2013–2019Patents assigned to GEN ELECTRIC (16)· patent assignee history
2013–2015Patents assigned to KASHYAP AVINASH SRIKRISHNAN (4)· patent assignee history
2013–2015Patents assigned to ANDARAWIS EMAD ANDARAWIS (3)· patent assignee history
2013–2014Patents assigned to SHADDOCK DAVID MULFORD (2)· patent assignee history
2013Patents assigned to ARTHUR STEPHEN DALEY (1)· patent assignee history
2013–2019Based in Clifton Park, NY, US· patent location history
2014–2019Based in Niskayuna, NY, US· patent location history
2018–2020Based in Portland, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| GEN ELECTRIC | 16 | 2013–2019 |
| KASHYAP AVINASH SRIKRISHNANself | 4 | 2013–2015 |
| ANDARAWIS EMAD ANDARAWIS | 3 | 2013–2015 |
| SHADDOCK DAVID MULFORD | 2 | 2013–2014 |
| ARTHUR STEPHEN DALEY | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Niskayuna, New York, US | 8 | 2014–2019 |
| Clifton Park, New York, US | 8 | 2013–2019 |
| Portland, OR, US | 2 | 2018–2020 |