LexDanaLexDanabeta
Inventor

Rui Huang

Inventor
Singapore, SG

Overview

90→
Patents
2008–2019
Patent span
Electricity
Primary field (CPC H)

Patents· 90 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1054%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
H01LSemiconductor devices13%
H10DInorganic electric semiconductor devices5%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems2%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation1%
B01JChemical or physical processes, e.g. catalysis or colloid chemistry1%
B82YSpecific uses or applications of nanostructures1%
C25CProcesses for the electrolytic production, recovery or refining of metals1%
C25DProcesses for the electrolytic or electrophoretic production of coatings1%
PatentTitleYear
10,354,934Semiconductor packages and methods of packaging semiconductor devices201910,170,385Semiconductor device and method of forming stacked vias within interconnect structure for FO-WLCSP20199,978,658Semiconductor packages and methods of packaging semiconductor devices20189,960,130Reliable interconnect20189,666,500'Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief'20179,620,557'Semiconductor device and method of forming EWLB semiconductor package with vertical interconnect structure and cavity region'20179,564,387'Semiconductor package having routing traces therein'20179,524,955'Semiconductor device and method of forming no-flow underfill material around vertical interconnect structure'20169,515,016'Semiconductor package and method of forming z-direction conductive posts embedded in structurally protective encapsulant'20169,508,623'Semiconductor packages and methods of packaging semiconductor devices'20169,385,009'Semiconductor device and method of forming stacked vias within interconnect structure for Fo-WLCSP'20169,293,350'Semiconductor package system with cavity substrate and manufacturing method therefor'20169,275,877'Semiconductor device and method of forming semiconductor package using panel form carrier'20169,257,356'Semiconductor device and method of forming an IPD beneath a semiconductor die with direct connection to external devices'20169,252,172'Semiconductor device and method of forming EWLB semiconductor package with vertical interconnect structure and cavity region'20169,236,278'Integrated circuit packaging system with a substrate embedded dummy-die paddle and method of manufacture thereof'20169,171,769'Semiconductor device and method of forming openings through encapsulant to reduce warpage and stress on semiconductor package'20159,162,222'Method for tuning surface structure of metallic nano-catalyst and preparation method thereof'20159,123,733'Integrated circuit packaging system with package underfill and method of manufacture thereof'20159,099,455'Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant'20159,087,930'Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief'20158,963,309'Semiconductor package with penetrable encapsulant joining semiconductor die and method thereof'20158,803,330'Integrated circuit package system with mounting structure'20148,790,962'Semiconductor device and method of forming a shielding layer over a semiconductor die after forming a build-up interconnect structure'20148,766,426'Integrated circuit packaging system with warpage control and method of manufacture thereof'20148,759,155'Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief'20148,723,305'Semiconductor package having semiconductor die with internal vertical interconnect structure and method therefor'20148,648,448'Semiconductor device and method of shielding semiconductor die from inter-device interference'20148,642,382'Integrated circuit packaging system with support structure and method of manufacture thereof'20148,624,364'Integrated circuit packaging system with encapsulation connector and method of manufacture thereof'20148,614,508'Integrated circuit system with test pads and method of manufacture thereof'20138,558,277'Semiconductor device and method of providing electrostatic discharge protection for integrated passive devices'20138,546,195'Semiconductor package having semiconductor die with internal vertical interconnect structure and method therefor'20138,507,319'Integrated circuit package system with shield'20138,492,204'Integrated circuit package-in-package system with wire-in-film encapsulant and method for manufacturing thereof'20138,487,434'Integrated circuit package system with redistribution layer and method for manufacturing thereof'20138,476,120'Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors'20138,455,991'Integrated circuit packaging system with warpage control and method of manufacture thereof'20138,456,002'Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief'20138,436,439'Semiconductor device and method of forming a shielding layer over a semiconductor die after forming a build-up interconnect structure'20138,421,212'Integrated circuit packaging system with active surface heat removal and method of manufacture thereof'20138,409,921'Integrated circuit package system including honeycomb molding'20138,405,228'Integrated circuit packaging system with package underfill and method of manufacture thereof'20138,404,518'Integrated circuit packaging system with package stacking and method of manufacture thereof'20138,399,305'Semiconductor device and method of forming dam material with openings around semiconductor die for mold underfill using dispenser and vacuum assist'20138,390,108'Integrated circuit packaging system with stacking interconnect and method of manufacture thereof'20138,368,188'Drop-mold conformable material as an encapsulation for an integrated circuit package system and method for manufacturing thereof'20138,368,199'Integrated circuit package system for stackable devices and method for manufacturing thereof'20138,354,304'Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant'20138,354,746'Semiconductor package and method of forming Z-direction conductive posts embedded in structurally protective encapsulant'20138,304,880'Integrated circuit packaging system with package-on-package and method of manufacture thereof'20128,299,596'Integrated circuit packaging system with bump conductors and method of manufacture thereof'20128,288,844'Integrated circuit packaging system with package stacking and method of manufacture thereof'20128,269,320'Integrated circuit package system for electromagnetic isolation and method for manufacturing thereof'20128,258,612'Encapsulant interposer system with integrated passive devices and manufacturing method therefor'20128,178,956'Integrated circuit package system for shielding electromagnetic interference'20128,163,597'Semiconductor device and method of forming no-flow underfill material around vertical interconnect structure'20128,159,047'Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors'20128,138,024'Package system for shielding semiconductor dies from electromagnetic interference'20128,138,590'Integrated circuit package system with wire-in-film encapsulation'20128,134,227'Stacked integrated circuit package system with conductive spacer'20128,101,460'Semiconductor device and method of shielding semiconductor die from inter-device interference'20128,084,302'Semiconductor package having semiconductor die with internal vertical interconnect structure and method therefor'20118,080,885'Integrated circuit packaging system with multi level contact and method of manufacture thereof'20118,076,757'Semiconductor device having electrical devices mounted to IPD structure and method of shielding electromagnetic interference'20118,072,059'Semiconductor device and method of forming UBM fixed relative to interconnect structure for alignment of semiconductor die'20118,049,314'Integrated circuit package system with insulator over circuitry'20118,048,776'Semiconductor device and method of supporting a wafer during backgrinding and reflow of solder bumps'20118,039,311'Leadless semiconductor chip carrier system'20117,993,941'Semiconductor package and method of forming Z-direction conductive posts embedded in structurally protective encapsulant'20117,989,270'Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors'20117,989,269'Semiconductor package with penetrable encapsulant joining semiconductor die and method thereof'20117,923,846'Integrated circuit package-in-package system with wire-in-film encapsulant'20117,902,644'Integrated circuit package system for electromagnetic isolation'20117,880,275'Semiconductor device and method of forming shielding along a profile disposed in peripheral region around the device'20117,863,109'Integrated circuit packaging system with a protrusion on an inner stacking module and method of manufacture thereof'20117,859,094'Integrated circuit package system for stackable devices'20107,843,047'Encapsulant interposer system with integrated passive devices and manufacturing method therefor'20107,834,430'Drop-mold conformable material as an encapsulation for an integrated circuit package system'20107,812,449'Integrated circuit package system with redistribution layer'20107,799,602'Semiconductor device and method of forming a shielding layer over a semiconductor die after forming a build-up interconnect structure'20107,772,046'Semiconductor device having electrical devices mounted to IPD structure and method for shielding electromagnetic interference'20107,772,080'Semiconductor device and method of providing electrostatic discharge protection for integrated passive devices'20107,732,252'Multi-chip package system incorporating an internal stacking module with support protrusions'20107,701,040'Semiconductor package and method of reducing electromagnetic interference between devices'20107,666,709'Semiconductor device and method of placing semiconductor die on a temporary carrier using fiducial patterns'20107,618,846'Semiconductor device and method of forming shielding along a profile disposed in peripheral region around the device'20097,615,910'High frequency surface acoustic wave device'20097,576,414'Electrostatic discharge (ESD) protection structure'20097,449,377'Method of fabricating poly silicon layer'2008

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2008Based in Kaohsiung, TW· patent location history
2009–2017Patents assigned to STATS CHIPPAC LTD (79)· patent assignee history
2009–2019Based in Singapore, SG· patent location history
2009Based in Taipei, TW· patent location history
2011–2016Patents assigned to HUANG RUI (53)· patent assignee history
2011–2016Patents assigned to CHOW SENG GUAN (36)· patent assignee history
2011–2016Patents assigned to KUAN HEAP HOE (35)· patent assignee history
2011–2016Patents assigned to LIN YAOJIAN (15)· patent assignee history
2015Based in Fujian, CN· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
STATS CHIPPAC LTD792009–2017
HUANG RUIself532011–2016
CHOW SENG GUAN362011–2016
KUAN HEAP HOE352011–2016
LIN YAOJIAN152011–2016
Locations
LocationPatentsSpan
Singapore, SG872009–2019
Fujian, CN12015
Taipei, TW12009
Kaohsiung, TW12008