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Inventor

Vinod Menezes

Inventor
Bangalore, IN

Overview

30→
Patents
1997–2020
Patent span
Physics
Primary field (CPC G)

Patents· 30 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores29%
G06FElectric digital data processing18%
H03KPulse technique12%
G01RMeasuring electric variables8%
G05FSystems for regulating electric or magnetic variables6%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems6%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
B41JTypewriters2%
G03GElectrography2%
PatentTitleYear
10,855,184Load current measurement202010,855,069USB type-C/PD controller having integrated VBUS to CC short protection202010,684,322Systems and methods of testing multiple dies202010,601,408Low frequency oscillator with ultra-low short circuit current202010,447,142Load current measurement201910,220,610Method of printing a print job with digital finishing visualization images201910,180,454Systems and methods of testing multiple dies201910,090,833Low power reset circuit201810,068,638Apparatus with low power SRAM retention mode201810,008,261Sense amplifier in low power and high performance SRAM20189,799,395'Sense amplifier in low power and high performance SRAM'20179,741,430'Static random access memory with reduced write power'20179,734,896'Circuits and methods for performance optimization of SRAM memory'20179,698,770'Low power reset circuit'20179,613,685'Burst mode read controllable SRAM'20179,571,104'Programmable body bias power supply'20179,384,826'Circuits and methods for performance optimization of SRAM memory'20169,236,113'Read assist for an SRAM using a word line suppression circuit'20169,218,892'Error prediction in logic and memory devices'20159,158,683'Multiport memory emulation using single-port memory devices'20159,082,507'Read assist circuit for an SRAM, including a word line suppression circuit'20158,812,885'Detecting wake-up events for a chip based on an I/O power supply'20148,762,804'Error prediction in logic and memory devices'20148,755,239'Read assist circuit for an SRAM'20148,379,465'Combined write assist and retain-till-accessed memory array bias'20136,876,594'Integrated circuit with programmable fuse array'20056,563,349'Multiplexor generating a glitch free output when selecting from multiple clock signals'20036,237,017'Lossy technique for image and speech processing'20016,084,444'Buffer driver reference circuit'20005,629,646'Apparatus and method for power reduction in dRAM units'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2020Patents assigned to TEXAS INSTRUMENTS INC (28)· patent assignee history
1997–2020Based in Bangalore, IN· patent location history
2003–2016Based in Karnataka, IN· patent location history
2013–2014Patents assigned to CLINTON MICHAEL PATRICK (2)· patent assignee history
2013–2014Patents assigned to HOLLA LAKSHMIKANTHA V (2)· patent assignee history
2013–2014Patents assigned to MENEZES VINOD (2)· patent assignee history
2014–2015Patents assigned to MENEZES VINOD JOSEPH (2)· patent assignee history
2014Based in 1st Cross Cooke Town, IN· patent location history
2019–2020Based in Bengaluru, IN· patent location history
2019Based in Venlo, NL· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TEXAS INSTRUMENTS INC281997–2020
CLINTON MICHAEL PATRICK22013–2014
HOLLA LAKSHMIKANTHA V22013–2014
MENEZES VINODself22013–2014
MENEZES VINOD JOSEPHself22014–2015
Locations
LocationPatentsSpan
Bangalore, IN221997–2020
Karnataka, IN42003–2016
Bengaluru, IN22019–2020
Venlo, NL12019
1st Cross Cooke Town, IN12014