Inventor

James A. McCall

Inventor

Portland, OR, US

Overview

73→

Patents

2002–2021

Patent span

Physics

Primary field (CPC G)

Patents· 73 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores24%

G06FElectric digital data processing22%

H05KPrinted circuits14%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use8%

H03KPulse technique7%

H04LTransmission of digital information, e.g. telegraphic communication6%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%

Y10TTechnical subjects covered by former us classification4%

H01RElectrically-conductive connections3%

H01LSemiconductor devices2%

PatentTitleYear

11,116,072Discrete circuit having cross-talk noise cancellation circuitry and method thereof2021 11,074,959DDR memory bus with a reduced data strobe signal preamble timespan2021 11,056,179Techniques to couple high bandwidth memory device on silicon substrate and package substrate2021 10,965,047Connector with active circuit2021 10,963,404High bandwidth DIMM2021 10,950,536Packed interconnect structure with reduced cross coupled noise2021 10,943,640Apparatus, method and system for providing termination for multiple chips of an integrated circuit package2021 10,884,958DIMM for a high bandwidth memory channel2021 10,839,887Applying chip select for memory device identification and power management control2020 10,802,996Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines2020 10,729,002Device, system and method to mitigate signal noise in communications with a memory module2020 10,617,000Printed circuit board (PCB) with three-dimensional interconnects to other printed circuit boards2020 10,592,445Techniques to access or operate a dual in-line memory module via multiple data channels2020 10,552,285Impedance compensation based on detecting sensor data2020 10,541,018DDR memory bus with a reduced data strobe signal preamble timespan2020 10,528,515Memory channel driver with echo cancellation2020 10,467,160Memory channel having more than one DIMM per motherboard DIMM connector2019 10,437,746Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines2019 10,146,711Techniques to access or operate a dual in-line memory module via multiple data channels2018 10,134,463Reconfigurable clocking architecture2018 10,121,528Apparatus, method and system for providing termination for multiple chips of an integrated circuit package2018 10,079,052Multiple rank high bandwidth memory2018 10,031,868Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines2018 10,033,382Method and apparatus for dynamic memory termination2018 10,025,685Impedance compensation based on detecting sensor data2018 9,934,842Multiple rank high bandwidth memory2018 9,786,353'Reconfigurable clocking architecture'2017 9,665,527'Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines'2017 9,596,766'Method of manufacturing a circuit board'2017 9,595,963'Method and apparatus for dynamic memory termination'2017 9,552,164'Apparatus, method and system for determining reference voltages for a memory'2017 9,384,164'Mapping memory controller connectors to memory connectors'2016 9,374,004'I/O driver transmit swing control'2016 9,240,250'Apparatus and method to reduce power delivery noise for partial writes'2016 9,218,575'Periodic training for unmatched signal receiver'2015 9,219,623'Adaptive delay base loss equalization'2015 9,153,296'Methods and apparatuses for dynamic memory termination'2015 9,152,257'Low swing voltage mode driver'2015 9,024,665'Transmitter with voltage and current mode drivers'2015 8,972,685'Method, apparatus and system for exchanging communications via a command/address bus'2015 8,673,391'Method of manufacturing a circuit board'2014 8,415,002'Method of manufacturing a circuit board'2013 8,274,308'Method and apparatus for dynamic memory termination'2012 7,772,708'Stacking integrated circuit dies'2010 7,694,060'Systems with variable link widths based on estimated activity levels'2010 7,676,917'Method of manufacturing a circuit board'2010 7,542,322'Buffered continuous multi-drop clock ring'2009 7,514,773'Systems and arrangements for interconnecting integrated circuit dies'2009 7,459,200'Circuit board design'2008 7,447,929'Countering power resonance'2008 7,446,572'Method and system for a configurable Vcc reference and Vss reference differential current mode transmitter'2008 7,246,022'Initiation of differential link retraining upon temperature excursion'2007 7,194,572'Memory system and method to reduce reflection and signal degradation'2007 7,133,962'Circulator chain memory command and address bus topology'2006 7,010,637'Single-ended memory interface system'2006 6,918,078'Systems with modules sharing terminations'2005 6,820,163'Buffering data transfer between a chipset and memory modules'2004 6,771,515'Systems having modules with on die terminations'2004 6,747,483'Differential memory interface system'2004 6,724,082'Systems having modules with selectable on die terminations'2004 6,717,823'Systems having modules with buffer chips'2004 6,711,640'Split delay transmission line'2004 6,711,027'Modules having paths of different impedances'2004 6,708,243'Computer assembly with stub traces coupled to vias to add capacitance at the vias'2004 6,700,457'Impedance compensation for circuit board breakout region'2004 6,686,762'Memory module using DRAM package to match channel impedance'2004 6,674,648'Termination cards and systems therefore'2004 6,674,649'Systems having modules sharing on module terminations'2004 6,631,083'Systems with modules and clocking therefore'2003 6,597,202'Systems with skew control between clock and data signals'2003 6,539,449'Capacitively loaded continuity module'2003 6,515,555'Memory module with parallel stub traces'2003 6,366,466'Multi-layer printed circuit board with signal traces of varying width'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2021Patents assigned to INTEL CORP (73)· patent assignee history

2002–2015Based in Beaverton, OR, US· patent location history

2009Based in Hillsboro, OR, US· patent location history

2012–2016Patents assigned to MCCALL JAMES A (8)· patent assignee history

2012–2016Patents assigned to BAINS KULJIT S (5)· patent assignee history

2012–2021Based in Portland, OR, US· patent location history

2013–2015Patents assigned to SHYKIND DAVID (3)· patent assignee history

2015Patents assigned to CHAUDHURI SANTANU (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	73	2002–2021
MCCALL JAMES Aself	8	2012–2016
BAINS KULJIT S	5	2012–2016
SHYKIND DAVID	3	2013–2015
CHAUDHURI SANTANU	1	2015

Locations

Location	Patents	Span
Portland, OR, US	41	2012–2021
Beaverton, OR, US	31	2002–2015
Hillsboro, OR, US	1	2009