Inventor
Tohru Tsujide
Inventor
Tokyo, JP
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1024%
G01RMeasuring electric variables20%
H01JElectric discharge tubes or discharge lamps16%
G01NInvestigating or analysing materials by determining their chemical or physical properties8%
G11CStatic stores8%
G21KHandling of particles or ionising radiation not otherwise provided for8%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
H10BElectronic memory devices4%
H10DInorganic electric semiconductor devices4%
G06FElectric digital data processing2%
PatentTitleYear
7,795,593'Surface contamination analyzer for semiconductor wafers'20107,700,380'Surface contamination analyzer for semiconductor wafers, method used therein and process for fabricating semiconductor device'20107,385,195'Semiconductor device tester'20087,321,805'Production managing system of semiconductor device'20086,975,125'Semiconductor device tester'20056,946,857'Semiconductor device tester'20056,943,043'Surface contamination analyzer for semiconductor wafers, method used therein and process for fabricating semiconductor device'20056,842,663'Production managing system of semiconductor device'20056,768,324'Semiconductor device tester which measures information related to a structure of a sample in a depth direction'20046,753,194'Surface contamination analyzer for semiconductor wafers, method used therein and process for fabricating semiconductor device'20046,711,453'Production managing system of semiconductor device'20046,614,244'Semiconductor device inspecting apparatus'20036,559,662'Semiconductor device tester and semiconductor device test method'20036,133,744'Apparatus for testing semiconductor wafer'20005,703,492'System and method for fault analysis of semiconductor integrated circuit'19975,532,610'Apparatus for testing semicondctor wafer'19965,521,516'Semiconductor integrated circuit fault analyzing apparatus and method therefor'19965,511,162'Automatic LSI testing apparatus using expert system'19964,733,285'Semiconductor device with input and/or output protective circuit'19884,590,508'MOS static ram with capacitively loaded gates to prevent alpha soft errors'19864,481,524'Semiconductor memory device having stacked polycrystalline silicon layers'19844,322,736'Short-resistant connection of polysilicon to diffusion'19824,310,900'Memory device with different read and write power levels'1982Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1982–1986Patents assigned to NIPPON ELECTRIC CO (4)· patent assignee history
1982–2010Based in Tokyo, JP· patent location history
1988–2000Patents assigned to NEC CORP (6)· patent assignee history
2003–2008Patents assigned to FAB SOLUTIONS INC (10)· patent assignee history
2008–2010Patents assigned to TOPCON CORP (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| FAB SOLUTIONS INC | 10 | 2003–2008 |
| NEC CORP | 6 | 1988–2000 |
| NIPPON ELECTRIC CO | 4 | 1982–1986 |
| TOPCON CORP | 3 | 2008–2010 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 23 | 1982–2010 |