Inventor
CHIA-PIN CHIU
Inventor
US
Overview
Patents· 40 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1033%
H01LSemiconductor devices31%
G02BOptical elements, systems or apparatus13%
H05KPrinted circuits5%
G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein3%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
H01RElectrically-conductive connections2%
G01JMeasurement of intensity, velocity, spectral content, polarisation, phase or pulse characteristics of infrared, visible or ultraviolet light1%
G06FElectric digital data processing1%
H01GCapacitors1%
PatentTitleYear
12,591,092Covered cavity for a photonic integrated circuit (PIC)202612,571,959Embedded photonic integrated circuits202612,541,055Electronic device including a lens assembly202612,504,580Reduced bridge structure for a photonic integrated circuit202512,443,058On-cavity photonic integrated circuit (OCPIC) to achieve the most undercut real estate for effective thermal tuning202512,442,982Temperature sensor to achieve thermal stabilization of micro-ring resonator (MRR) in an open cavity photonic integrated circuit (OCPIC)202512,436,413Undercut design with a bonded base cover for friendly assembly and effective thermal tuning of micro-ring resonator (MRR) in open cavity photonic integrated chips (OCPIC)202512,366,713Heat dissipation structures for optical communication devices202512,327,807High density substrate routing in package202512,308,299TEC-embedded dummy die to cool the bottom die edge hotspot202512,293,956Boiling enhancement structures for immersion cooled electronic systems202512,191,220Hybrid interposer of glass and silicon to reduce thermal crosstalk202512,176,676Package designs to enable dual-sided cooling on a laser chip202412,113,026Multi-chip package and method of providing die-to-die interconnects in same202412,107,042Localized high density substrate routing202412,099,245Completely encapsulated optical multi chip package202412,094,800Thermally conductive slugs/active dies to improve cooling of stacked bottom dies202412,051,667High density substrate routing in package202412,009,321Package system and package202411,984,396Localized high density substrate routing202411,876,053Multi-chip package and method of providing die-to-die interconnects in same202411,854,931STIM/liquid metal filled laser drill trench to improve cooling of stacked bottom die202311,837,519Heatsink cutout and insulating through silicon vias to cut thermal cross-talk202311,824,008Multi-chip package and method of providing die-to-die interconnects in same202311,810,884High density substrate routing in package202311,670,5613D buildup of thermally conductive layers to resolve die height differences202311,652,020Thermal solutions for multi-package assemblies and methods for fabricating the same202311,646,244Socket loading mechanism for passive or active socket and package cooling202311,579,426Dual collimating lens configuration for optical devices202311,581,671Integrated circuit package socket housing to enhance package cooling202311,551,994Liquid metal TIM with STIM-like performance with no BSM and BGA compatible202311,521,914Microelectronic assemblies having a cooling channel202211,515,248Localized high density substrate routing202211,515,232Liquid cooling through conductive interconnect202211,456,232Thermal assemblies for multi-chip packages202211,444,003Integrated heat spreader with multiple channels for multichip packages202211,398,414Sloped metal features for cooling hotspots in stacked-die packages202211,251,150High density substrate routing in package202211,156,815Compound parabolic concentrator including protrusion202111,140,770Printed circuit board assembly2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to INTEL CORP (40)· patent assignee history
2021–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 40 | 2021–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 40 | 2021–2026 |