Inventor
Andrew David Tune
Inventor
Dronfield, GB
Overview
Patents· 44 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing67%
H04LTransmission of digital information, e.g. telegraphic communication17%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
H03KPulse technique3%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%
G06NComputing arrangements based on specific computational models2%
H01PWaveguides2%
H04JMultiplex communication2%
PatentTitleYear
10,956,205Data processing202110,938,622Interconnection network for integrated circuit with fault detection circuitry provided locally to an upstream location202110,929,060Data access request specifying enable vector202110,771,194Interconnection network for integrated circuit202010,761,561Error checking for primary signal transmitted between first and second clock domains202010,740,269Arbitration circuitry202010,592,439Arbitrating circuitry and method202010,579,469Interconnection network for integrated circuit202010,489,323Data processing system for a home node to authorize a master to bypass the home node to directly send data to a slave201910,303,624Arbitrating and multiplexing circuitry201910,289,587Switching device using buffering201910,185,667Storage controller201910,169,236Cache coherency20199,977,742Cache coherency20189,928,195'Interconnect and method of operation of an interconnect for ordered write observation (OWO)'20189,906,440'Arbitrating and multiplexing circuitry'20189,892,072'Transaction response modification within interconnect circuitry'20189,852,088Hazard checking control within interconnect circuitry20179,727,466'Interconnect and method of managing a snoop filter for an interconnect'20179,639,470'Coherency checking of invalidate transactions caused by snoop filter eviction in an integrated circuit'20179,632,955'Reorder buffer permitting parallel processing operations with repair on ordering hazard detection within interconnect circuitry'20179,507,716'Coherency checking of invalidate transactions caused by snoop filter eviction in an integrated circuit'20169,507,737'Arbitration circuitry and method'20169,442,878'Parallel snoop and hazard checking with interconnect circuitry'20169,361,236'Handling write requests for a data array'20169,311,244'Enforcing ordering of snoop transactions in an interconnect for an integrated circuit'20169,304,923'Data coherency management'20169,300,716'Modelling dependencies in data traffic'20169,294,301'Selecting between contending data packets to limit latency differences between sources'20169,213,660'Receiver based communication permission token allocation'20159,176,856'Data store and method of allocating data to the data store'20159,170,979'Converging interconnect node controlling operation related to associated future item in dependence upon data predicted based on current transaction data item passing through'20158,892,801'Arbitration circuity and method for arbitrating between a plurality of requests for access to a shared resource'20148,819,309'Low latency bypass buffer'20148,619,554'Interconnecting initiator devices and recipient devices'20138,307,138'Apparatus and method for controlling issuing of transaction requests'20128,291,244'Power management in a data processing device having masters and slaves'20128,285,912'Communication infrastructure for a data processing apparatus and a method of operation of such a communication infrastructure'20128,266,482'Operating parameter control for integrated circuit signal paths'20128,171,191'Bus interconnect device and a data processing apparatus including such a bus interconnect device'20127,945,806'Data processing apparatus and method for controlling a transfer of payload data over a communication channel'20117,809,972'Data processing apparatus and method for translating a signal between a first clock domain and a second clock domain'20107,664,901'Data processing apparatus and method for arbitrating access to a shared resource'20107,149,862'Access control in a data processing apparatus'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2021Patents assigned to ADVANCED RISC MACH LTD (44)· patent assignee history
2006–2021Based in Dronfield, GB· patent location history
2012–2016Patents assigned to TUNE ANDREW DAVID (10)· patent assignee history
2012–2016Patents assigned to BRUCE ALISTAIR CRONE (3)· patent assignee history
2012–2013Patents assigned to HOTCHKISS ROBIN (2)· patent assignee history
2012Based in Derbyshire, GB· patent location history
2014–2021Based in Sheffield, GB· patent location history
2015–2016Patents assigned to SALISBURY SEAN JAMES (2)· patent assignee history
2016Based in Cambridge, GB· patent location history
2017Based in Gratkorn, AT· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED RISC MACH LTD | 44 | 2006–2021 |
| TUNE ANDREW DAVIDself | 10 | 2012–2016 |
| BRUCE ALISTAIR CRONE | 3 | 2012–2016 |
| HOTCHKISS ROBIN | 2 | 2012–2013 |
| SALISBURY SEAN JAMES | 2 | 2015–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Dronfield, GB | 24 | 2006–2021 |
| Sheffield, GB | 17 | 2014–2021 |
| Gratkorn, AT | 1 | 2017 |
| Cambridge, GB | 1 | 2016 |
| Derbyshire, GB | 1 | 2012 |