Inventor
Rajat Agarwal
Inventor
Beaverton, OR, US
Overview
Patents· 40 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing46%
G11CStatic stores19%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use10%
H03MCoding6%
H01LSemiconductor devices4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
H04LTransmission of digital information, e.g. telegraphic communication2%
H05KPrinted circuits2%
Y10TTechnical subjects covered by former us classification2%
G05BControl or regulating systems in general1%
PatentTitleYear
10,877,897System, apparatus and method for multi-cacheline small object memory tagging202010,872,011Internal error checking and correction (ECC) with extra system bits202010,725,861Error correction code memory security202010,719,443Apparatus and method for implementing a multi-level memory hierarchy202010,594,491Cryptographic system memory management202010,593,019Method and apparatus for storing, processing and reconstructing full resolution image out of sub band encoded images202010,579,464Method and apparatus for partial cache line sparing202010,459,809Stacked memory chip device with enhanced data protection capability201910,417,135Near memory miss prediction to reduce memory access latency201910,409,727System, apparatus and method for selective enabling of locality-based instruction handling201910,402,336System, apparatus and method for overriding of non-locality-based instruction handling201910,296,457Reducing conflicts in direct mapped caches201910,275,001Thermal throttling of electronic devices201910,241,912Apparatus and method for implementing a multi-level memory hierarchy201910,198,354Apparatus, system, and method to flush modified data from a volatile memory to a persistent second memory201910,102,126Apparatus and method for implementing a multi-level memory hierarchy having different operating modes20189,910,728'Method and apparatus for partial cache line sparing'20189,691,505'Dynamic application of error correction code (ECC) based on error type'20179,646,910'Integrated heat spreader that maximizes heat transfer from a multi-chip package'20179,613,722'Method and apparatus for reverse memory sparing'20179,600,416'Apparatus and method for implementing a multi-level memory hierarchy'20179,378,142'Apparatus and method for implementing a multi-level memory hierarchy having different operating modes'20169,257,364'Integrated heat spreader that maximizes heat transfer from a multi-chip package'20169,195,551'Enhanced storage of metadata utilizing improved error detection and correction in computer memory'20159,043,674'Error detection and correction apparatus and method'20158,964,580'Device topology and capability discovery and reporting techniques'20158,612,832'Mechanisms and techniques for providing cache tags in dynamic random access memory'20138,438,452'Poison bit error checking code scheme'20138,239,737'Data line storage and transmission utilizing both error correcting code and synchronization information'20128,122,265'Power management using adaptive thermal throttling'20128,069,327'Commands scheduled for frequency mismatch bubbles'20118,060,692'Memory controller using time-staggered lockstep sub-channels with buffered memory'20118,041,898'Method, system and apparatus for reducing memory traffic in a distributed memory system'20117,941,618'Fully buffered DIMM read data substitution for write acknowledgement'20117,734,980'Mitigating silent data corruption in a buffered memory module architecture'20107,644,248'Mechanism to generate logically dedicated read and write channels in a memory controller'20107,644,347'Silent data corruption mitigation using error correction code with embedded signaling fault detection'20107,587,625'Memory replay mechanism'20097,516,349'Synchronized memory channels with unidirectional links'20097,444,479'Fully buffered DIMM read data substitution for write acknowledgement'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2017Patents assigned to AGARWAL RAJAT (12)· patent assignee history
2008–2017Patents assigned to CHENG KAI (2)· patent assignee history
2008–2011Patents assigned to CHRISTENSON BRUCE A (2)· patent assignee history
2008–2020Based in Beaverton, OR, US· patent location history
2009–2020Patents assigned to INTEL CORP (37)· patent assignee history
2012–2015Patents assigned to HUDDLESTON C SCOTT (3)· patent assignee history
2015Based in San Jose, CA, US· patent location history
2019–2020Based in Portland, OR, US· patent location history
2020Based in Dehradun, IN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 37 | 2009–2020 |
| AGARWAL RAJATself | 12 | 2008–2017 |
| HUDDLESTON C SCOTT | 3 | 2012–2015 |
| CHENG KAI | 2 | 2008–2017 |
| CHRISTENSON BRUCE A | 2 | 2008–2011 |
Locations
| Location | Patents | Span |
|---|---|---|
| Beaverton, OR, US | 35 | 2008–2020 |
| Portland, OR, US | 3 | 2019–2020 |
| Dehradun, IN | 1 | 2020 |
| San Jose, California, US | 1 | 2015 |