Inventor
Fabio Pellizzer
Inventor
Boise, ID, US
Overview
Patents· 207 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices24%
H10NElectric solid-state devices not otherwise provided for24%
G11CStatic stores19%
H01LSemiconductor devices18%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
H10DInorganic electric semiconductor devices6%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%
G01NInvestigating or analysing materials by determining their chemical or physical properties0%
H03KPulse technique0%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests0%
PatentTitleYear
11,133,463Memory cells with asymmetrical electrode interfaces202111,133,062Two memory cells sensed to determine one data value202111,120,870Mixed cross point memory202111,114,613Cross-point memory and methods for forming of the same202111,094,377Multi-level self-selecting memory device202111,069,610Methods for forming microelectronic devices with self-aligned interconnects, and related devices and systems202111,049,769Self-aligned interconnection for integrated circuits202111,043,277Two multi-level memory cells sensed to determine multiple data values202111,031,553Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact cross references202111,018,300Self-aligned memory decks in cross-point memory arrays202111,018,190Three-dimensional memory apparatuses and methods of use202110,998,379Three dimensional memory arrays202110,950,284Vertical decoder202110,943,657Mitigation of voltage threshold drift associated with power down condition of non-volatile memory device202110,937,829Three dimensional memory arrays202110,930,707Memory device with a split pillar architecture202110,910,438Memory array with graded memory stack resistances202110,896,932Three dimensional memory array202110,868,248Tapered memory cell profiles202010,854,674Cross-point memory and methods for fabrication of same202010,803,939Techniques for programming a memory cell202010,803,934Mixed cross point memory202010,777,291Drift mitigation with embedded refresh202010,777,266Mixed cross point memory202010,748,615Polarity-conditioned memory cell write operations202010,734,446Three-dimensional memory apparatuses and methods of use202010,720,579Self-selecting memory cell with dielectric barrier202010,707,271Memory cells having resistors and formation of the same202010,680,170Cross-point memory and methods for forming of the same202010,680,037Cross-point memory and methods for fabrication of same202010,672,981Memory cells with asymmetrical electrode interfaces202010,672,833Semiconductor devices including a passive material between memory cells and conductive access lines, and related electronic devices202010,665,298Techniques to access a self-selecting memory device202010,658,035Apparatuses and methods of reading memory cells202010,629,261Enhancing nucleation in phase-change memory cells202010,629,651Three-dimensional memory apparatus and method of manufacturing the same202010,622,558Non-volatile memory cell structures including a chalcogenide material having a narrowed end and a three-dimensional memory device202010,622,408Resistive memory cell structures and methods202010,600,481Apparatuses including memory cells and methods of operation of same202010,593,399Self-selecting memory array with horizontal bit lines202010,580,980Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact cross references202010,559,337Vertical decoder202010,546,632Multi-level self-selecting memory device202010,541,364Memory cells with asymmetrical electrode interfaces202010,510,957Self-aligned memory decks in cross-point memory arrays201910,497,753Three dimensional memory array201910,497,863Method, system, and device for L-shaped memory component201910,490,602Three dimensional memory arrays201910,483,463Memory cells, memory arrays, and methods of forming memory cells and arrays201910,482,954Phase change memory device201910,461,125Three dimensional memory arrays201910,460,798Memory cells having a plurality of resistance variable materials201910,446,226Apparatuses including multi-level memory cells and methods of operation of same201910,431,739Clamp elements for phase change memory arrays201910,424,728Self-selecting memory cell with dielectric barrier201910,424,374Programming enhancement in self-selecting memory201910,424,618Array of cross point memory cells and methods of forming an array of cross point memory cells201910,424,730Tapered memory cell profiles201910,410,718Apparatuses and methods for current limitation in threshold switching memories201910,396,125Cross-point memory and methods for fabrication of same201910,381,075Techniques to access a self-selecting memory device201910,354,729Polarity-conditioned memory cell write operations201910,283,703Cross-point memory and methods for forming of the same201910,283,198Apparatuses and methods of reading memory cells based on response to a test pulse201910,276,235Enhancing nucleation in phase-change memory cells201910,269,442Drift mitigation with embedded refresh201910,263,039Memory cells having resistors and formation of the same201910,255,975Apparatuses and methods of reading memory cells201910,186,659Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact cross references201910,163,506Apparatuses including memory cells and methods of operation of same201810,163,982Multi-deck memory device with inverted deck201810,157,670Apparatuses including memory cells and methods of operation of same201810,157,788Self-aligned interconnection for integrated circuits201810,157,667Mixed cross point memory201810,153,433Methods of forming memory cells201810,153,040Apparatuses and methods for current limitation in threshold switching memories201810,147,763Resistive memory cell structures and methods201810,141,508Clamp elements for phase change memory arrays201810,102,905Memory cells having a plurality of resistance variable materials201810,096,655Three dimensional memory array201810,062,433Apparatuses and methods of reading memory cells20189,990,989Enhancing nucleation in phase-change memory cells20189,978,810Three-dimensional memory apparatuses and methods of use20189,947,720Three-dimensional memory apparatuses and methods of use20189,935,154Resistive memory cell structures and methods20189,917,253'Methods of forming memory arrays'20189,899,451'Array of cross point memory cells and methods of forming an array of cross point memory cells'20189,876,166Phase change memory cell and manufacturing method thereof using minitrenches20189,876,168Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact cross references20189,870,820'Apparatuses and methods for current limitation in threshold switching memories'20189,806,129'Cross-point memory and methods for fabrication of same'20179,786,719'Method for base contact layout, such as for memory'20179,779,805'Phase change memory device'20179,768,378'Cross-point memory and methods for fabrication of same'20179,755,145'Memory arrays having confined phase change material structures laterally surrounded with silicon nitride'20179,748,311'Cross-point memory and methods for fabrication of same'20179,705,080'Forming self-aligned conductive lines for resistive random access memories'20179,698,345'Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact cross references'20179,679,641'Memory cells having a plurality of resistance variable materials'20179,673,393'Methods of forming memory arrays'20179,672,908'Apparatuses and methods of reading memory cells based on response to a test pulse'20179,645,102'Material test structure'20179,634,063'Method, system and device for recessed contact in memory array'20179,627,052'Apparatuses and methods for current limitation in threshold switching memories'20179,620,713'Memory cells formed with sealing material'20179,613,902'Connections for memory electrode lines'20179,608,042'Electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques'20179,570,167'Apparatuses and methods of reading memory cells'20179,570,681'Resistive random access memory'20179,525,007'Phase change memory device with voltage control elements'20169,520,555'Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact'20169,520,554'Clamp elements for phase change memory arrays'20169,520,190'Modified reset state for enhanced read margin of phase change memory'20169,484,536'Memory cells, memory arrays, and methods of forming memory cells and arrays'20169,460,784'Reference voltage generation apparatuses and methods'20169,449,683'Memory cells having a plurality of resistance variable materials'20169,443,562'Connections for memory electrode lines'20169,444,043'Method, system and device for phase change memory with shunt'20169,419,056'Resistive memory cell structures and methods'20169,362,494'Array of cross point memory cells and methods of forming an array of cross point memory cells'20169,343,676'Heating phase change material'20169,343,506'Memory arrays with polygonal memory cells having specific sidewall orientations'20169,343,149'Enhancing nucleation in phase-change memory cells'20169,343,670'Memory arrays and methods of forming same'20169,324,945'Memory cells and methods of forming memory cells'20169,318,699'Resistive memory cell structures and methods'20169,299,747'Electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques'20169,275,730'Apparatuses and methods of reading memory cells based on response to a test pulse'20169,269,747'Self-aligned interconnection for integrated circuits'20169,263,674'ETCH bias homogenization'20169,245,927'Semiconductor constructions, memory cells and memory arrays'20169,231,103'Vertical MOSFET transistor, in particular operating as a selector in nonvolatile memory devices'20169,224,635'Connections for memory electrode lines'20159,196,530'Forming self-aligned conductive lines for resistive random access memories'20159,172,037'Combined conductive plug/conductive line memory arrays and methods of forming the same'20159,136,307'Memory cells and memory cell formation methods using sealing material'20159,111,856'Method for fabricating a phase-change memory cell'20159,111,857'Method, system and device for recessed contact in memory array'20159,112,150'Methods of forming memory cells and arrays'20159,064,565'Phase change memory device'20158,988,926'Method, system and device for phase change memory with shunt'20158,976,570'Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact'20158,975,148'Memory arrays and methods of forming memory cells'20158,964,448'Memory cells having a plurality of resistance variable materials'20158,945,403'Material test structure'20158,921,196'Double patterning method for creating a regular array of pillars with dual shallow trench isolation'20148,908,414'Modified reset state for enhanced read margin of phase change memory'20148,885,382'Compact socket connection to cross-point array'20148,860,223'Resistive random access memory'20148,853,665'Semiconductor constructions, memory cells, memory arrays and methods of forming memory cells'20148,785,314'Etch bias homogenization'20148,766,344'Vertical mosfet transistor, in particular operating as a selector in nonvolatile memory devices'20148,743,598'Reversing a potential polarity for reading phase-change cells to shorten a recovery delay after programming'20148,728,940'Memory arrays and methods of forming same'20148,716,059'Combined conductive plug/conductive line memory arrays and methods of forming the same'20148,686,394'Semiconductor constructions and memory arrays'20148,653,495'Heating phase change material'20148,599,599'Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact'20138,553,453'Phase change memory device'20138,546,231'Memory arrays and methods of forming memory cells'20138,546,778'Resistance variable memory cells and methods'20138,536,013'Forming phase change memory cells'20138,410,527'Electrical fuse device based on a phase-change memory element and corresponding programming method'20138,358,532'Word-line driver including pull-up resistor and pull-down transistor'20138,293,598'Process for manufacturing a memory device including a vertical bipolar junction transistor and a CMOS transistor with spacers'20128,283,234'Memory including bipolar junction transistor select devices'20128,243,497'Phase change memory device with reduced programming disturbance'20128,084,789'Phase change memory with ovonic threshold switch'20118,076,211'Fabricating bipolar junction select transistors for semiconductor memories'20117,993,957'Phase change memory cell and manufacturing method thereof using minitrenches'20117,985,959'Self-aligned vertical bipolar junction transistor for phase change memories'20117,973,302'Forming phase change memory cells'20117,898,848'Memory including bipolar junction transistor select devices'20117,875,513'Self-aligned bipolar junction transistors'20117,872,326'Array of vertical bipolar junction transistors, in particular selectors in a phase change memory device'20117,847,373'Fabricating bipolar junction select transistors for semiconductor memories'20107,847,329'Vertical MOSFET transistor, in particular operating as a selector in nonvolatile memory devices'20107,687,830'Phase change memory with ovonic threshold switch'20107,639,526'Method for multilevel programming of phase change memory cells using a percolation algorithm'20097,618,840'Sublithographic contact structure, in particular for a phase change memory cell, and fabrication process thereof'20097,606,056'Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array thereby manufactured'20097,563,684'Process for manufacturing an array of cells including selection bipolar junction transistors'20097,560,782'Transistor structure with high input impedance and high current capability'20097,534,625'Phase change memory with damascene memory element'20097,515,460'Multilevel programming of phase change memory cells'20097,483,296'Memory device with unipolar and bipolar selectors'20097,446,011'Array of cells including a selection bipolar transistor and fabrication method thereof'20087,439,536'Phase change memory cell with tubular heater and manufacturing method thereof'20087,436,692'Phase change memory cell with junction selector and manufacturing method thereof'20087,422,926'Self-aligned process for manufacturing phase change memory cells'20087,402,455'Manufacturing method of a contact structure and phase change memory cell with elimination of double contacts'20087,391,642'Multilevel programming of phase change memory cells'20087,372,166'Sublithographic contact structure, phase change memory cell with optimized heater shape, and manufacturing method thereof'20087,307,451'Field programmable gate array device'20077,244,956'Self-aligned process for manufacturing a phase change memory cell and phase change memory cell thereby manufactured'20077,227,171'Small area contact region, high efficiency phase change memory cell and fabrication method thereof'20077,227,765'Content addressable memory cell'20077,135,696'Phase change memory with damascene memory element'20067,135,756'Array of cells including a selection bipolar transistor and fabrication method thereof'20067,122,824'Sublithographic contact structure, in particular for a phase change memory cell, and fabrication process thereof'20067,075,841'Writing circuit for a phase change memory device'20066,989,580'Process for manufacturing an array of cells including selection bipolar junction transistors'20066,974,734'Process for manufacturing a memory device, in particular a phase change memory, including a silicidation step'20056,972,430'Sublithographic contact structure, phase change memory cell with optimized heater shape, and manufacturing method thereof'20056,930,913'Contact structure, phase change memory cell, and manufacturing method thereof with elimination of double contacts'20056,891,747'Phase change memory cell and manufacturing method thereof using minitrenches'20056,816,404'Architecture of a phase-change nonvolatile memory array'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2018Patents assigned to OVONYX INC (17)· patent assignee history
2004–2013Patents assigned to ST MICROELECTRONICS SRL (13)· patent assignee history
2004–2018Based in Follina, IT· patent location history
2008–2018Patents assigned to PELLIZZER FABIO (45)· patent assignee history
2008–2014Patents assigned to PIROVANO AGOSTINO (15)· patent assignee history
2010–2021Based in Cornate d'Adda, IT· patent location history
2011–2021Patents assigned to MICRON TECHNOLOGY INC (154)· patent assignee history
2014–2021Based in Boise, ID, US· patent location history
2018Based in Canonica d'Adda, IT· patent location history
2021Based in Pozzo d'Adda, IT· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 154 | 2011–2021 |
| PELLIZZER FABIOself | 45 | 2008–2018 |
| OVONYX INC | 17 | 2004–2018 |
| PIROVANO AGOSTINO | 15 | 2008–2014 |
| ST MICROELECTRONICS SRL | 13 | 2004–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Boise, ID, US | 102 | 2014–2021 |
| Cornate d'Adda, IT | 63 | 2010–2021 |
| Follina, IT | 40 | 2004–2018 |
| Pozzo d'Adda, IT | 1 | 2021 |
| Canonica d'Adda, IT | 1 | 2018 |