Inventor
Tadao Aikawa
Inventor
Kawasaki, JP
Overview
Patents· 26 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores64%
H04LTransmission of digital information, e.g. telegraphic communication10%
H03KPulse technique8%
H10BElectronic memory devices8%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
H10DInorganic electric semiconductor devices3%
PatentTitleYear
7,907,434'Semiconductor apparatus having a large-size bus connection'20117,808,806'Semiconductor apparatus having a large-size bus connection'20107,317,241'Semiconductor apparatus having a large-size bus connection'20087,193,431'Resistance compensation method, circuit having a resistance compensation function, and circuit resistance test method'20076,735,101'Semiconductor memory'20046,727,533'Semiconductor apparatus having a large-size bus connection'20046,715,115'Semiconductor integrated circuit device capable of outputting leading data of a series of multiple burst-readout data without delay'20046,496,430'Semiconductor memory circuit having selective redundant memory cells'20026,459,641'Semiconductor memory device'20026,427,197'Semiconductor memory device operating in synchronization with a clock signal for high-speed data write and data read operations'20026,400,617'Semiconductor memory circuit having selective redundant memory cells'20026,388,945'Semiconductor memory device outputting data according to a first internal clock signal and a second internal clock signal'20026,377,513'Method for writing data to semiconductor memory and semiconductor memory'20026,333,890'Memory device with a plurality of common data buses'20016,246,620'Semiconductor memory device'20016,191,999'Semiconductor memory device with reduced power consumption'20016,192,004'Semiconductor integrated circuit'20016,188,640'Data output circuits for semiconductor memory devices'20016,185,149'Semiconductor integrated circuit memory'20016,166,964'Semiconductor memory and method of controlling data therefrom'20006,154,405'Semiconductor memory device having a dummy cell resetting the bit lines to a reset potential that is based on data read in a previous read data'20006,125,065'Semiconductor memory with column gates and method of controlling column gates during a write mask operation'20006,088,291'Semiconductor memory device'20005,978,884'Semiconductor memory device having a single line data bus and latch circuits for improved pipeline operations'19995,889,725'Decoder circuit for a semiconductor memory device'19995,874,853'Semiconductor integrated circuit system'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2008Patents assigned to FUJITSU LTD (24)· patent assignee history
1999–2011Based in Kawasaki, JP· patent location history
1999Based in Kanagawa, JP· patent location history
2011Patents assigned to FUJITSU SEMICONDUCTOR LTD (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| FUJITSU LTD | 24 | 1999–2008 |
| FUJITSU SEMICONDUCTOR LTD | 1 | 2011 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kawasaki, JP | 25 | 1999–2011 |
| Kanagawa, JP | 1 | 1999 |