Inventor
Jayavel Pachamuthu
Inventor
San Jose, CA, US
Overview
Patents· 94 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices27%
H01LSemiconductor devices27%
H10DInorganic electric semiconductor devices19%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
G11CStatic stores7%
G01RMeasuring electric variables1%
G06FElectric digital data processing1%
B05DProcesses for applying fluent materials to surfaces, in general0%
B23PMetal-working not otherwise provided for0%
PatentTitleYear
11,107,540Program disturb improvements in multi-tier memory devices including improved non-data conductive gate implementation202111,101,284Three-dimensional memory device containing etch stop structures and methods of making the same202111,037,631Column erasing in non-volatile memory strings202111,024,645Three-dimensional memory device containing a silicon nitride ring in an opening in a memory film and method of making the same202110,991,705Three-dimensional memory device having enhanced contact between polycrystalline channel and epitaxial pedestal structure and method of making the same202110,991,706Three-dimensional memory device having enhanced contact between polycrystalline channel and epitaxial pedestal structure and method of making the same202110,991,718Three-dimensional memory device containing a vertical semiconductor channel containing a connection strap and method of making the same202110,943,662Different word line programming orders in non-volatile memory for error recovery202110,861,559Controlled string erase for nonvolatile memory202010,763,271Three-dimensional memory device containing aluminum-silicon word lines and methods of manufacturing the same202010,475,879Support pillar structures for leakage reduction in a three-dimensional memory device and methods of making the same201910,381,434Support pillar structures for leakage reduction in a three-dimensional memory device201910,128,257Select transistors with tight threshold voltage in 3D memory201810,121,794Three-dimensional memory device having epitaxial germanium-containing vertical channel and method of making thereof201810,115,459Multiple liner interconnects for three dimensional memory devices and method of making thereof201810,103,161Offset backside contact via structures for a three-dimensional memory device201810,032,524Techniques for determining local interconnect defects201810,014,316Three-dimensional memory device with leakage reducing support pillar structures and method of making thereof20189,953,717NAND structure with tier select gate transistors20189,941,293Select transistors with tight threshold voltage in 3D memory20189,941,295Method of making a three-dimensional memory device having a heterostructure quantum well channel20189,934,872Erase stress and delta erase loop count methods for various fail modes in non-volatile memory20189,917,093'Inter-plane offset in backside contact via structures for a three-dimensional memory device'20189,881,929'Multi-tier memory stack structure containing non-overlapping support pillar structures and method of making thereof'20189,876,025Methods for manufacturing ultrathin semiconductor channel three-dimensional memory devices20189,870,945'Crystalline layer stack for forming conductive layers in a three-dimensional memory structure'20189,859,298'Amorphous silicon layer in memory device which reduces neighboring word line interference'20189,842,851'Three-dimensional memory devices having a shaped epitaxial channel portion'20179,830,998Stress patterns to detect shorts in three dimensional non-volatile memory20179,831,118Reducing neighboring word line in interference using low-k oxide20179,825,051'Three dimensional NAND device containing fluorine doped layer and method of making thereof'20179,799,669'Single-semiconductor-layer channel in a memory opening for a three-dimensional non-volatile memory device'20179,799,671'Three-dimensional integration schemes for reducing fluorine-induced electrical shorts'20179,793,283'High conductivity channel for 3D memory'20179,780,108'Ultrathin semiconductor channel three-dimensional memory devices'20179,761,604'3D vertical NAND with III-V channel'20179,754,958'Three-dimensional memory devices having a shaped epitaxial channel portion and method of making thereof'20179,748,267'Three dimensional NAND device with channel contacting conductive source line and method of making thereof'20179,698,152'Three-dimensional memory structure with multi-component contact via structure and method of making thereof'20179,685,454'Method of forming 3D vertical NAND with III-V channel'20179,666,590'High stack 3D memory and method of making'20179,666,593'Alternating refractive index in charge-trapping film in three-dimensional memory'20179,666,594'Multi-charge region memory cells for a vertical NAND device'20179,659,956'Three-dimensional memory device containing source select gate electrodes with enhanced electrical isolation'20179,627,403'Multilevel memory stack structure employing support pillar structures'20179,583,500'Multilevel memory stack structure and methods of manufacturing the same'20179,564,219'Current based detection and recording of memory hole-interconnect spacing defects'20179,559,117'Three-dimensional non-volatile memory device having a silicide source line and method of making thereof'20179,543,320'Three-dimensional memory structure having self-aligned drain regions and methods of making thereof'20179,530,514'Select gate defect detection'20169,524,981'Three dimensional memory device with hybrid source electrode for wafer warpage reduction'20169,524,976'Method of integrating select gate source and memory hole for three-dimensional non-volatile memory device'20169,520,406'Method of making a vertical NAND device using sequential etching of multilayer stacks'20169,515,085'Vertical memory device with bit line air gap'20169,496,274'Three-dimensional non-volatile memory device'20169,478,495'Three dimensional memory device containing aluminum source contact via structure and method of making thereof'20169,460,931'High aspect ratio memory hole channel contact formation'20169,455,263'Three dimensional NAND device with channel contacting conductive source line and method of making thereof'20169,449,985'Memory cell with high-k charge trapping layer'20169,449,982'Method of making a vertical NAND device using a sacrificial layer with air gap and sequential etching of multilayer stacks'20169,449,981'Three dimensional NAND string memory devices and methods of fabrication thereof'20169,443,865'Fabricating 3D NAND memory having monolithic crystalline silicon vertical NAND channel'20169,443,861'Fluorine-blocking insulating spacer for backside contact structure of three-dimensional memory structures'20169,437,606'Method of making a three-dimensional memory array with etch stop'20169,425,299'Three-dimensional memory device having a heterostructure quantum well channel'20169,419,135'Three dimensional NAND device having reduced wafer bowing and method of making thereof'20169,406,690'Contact for vertical memory with dopant diffusion stopper and associated fabrication method'20169,368,509'Three-dimensional memory structure having self-aligned drain regions and methods of making thereof'20169,368,510'Method of forming memory cell with high-k charge trapping layer'20169,356,031'Three dimensional NAND string memory devices with voids enclosed between control gate electrodes'20169,331,093'Three dimensional NAND device with silicon germanium heterostructure channel'20169,287,290'3D memory having crystalline silicon NAND string channel'20169,269,446'Methods to improve programming of slow cells'20169,240,249'AC stress methods to screen out bit line defects'20169,236,131'Bias to detect and prevent short circuits in three-dimensional memory device'20169,230,987'Multilevel memory stack structure and methods of manufacturing the same'20169,230,982'Protective structure to prevent short circuits in a three-dimensional memory device'20169,230,974'Methods of selective removal of blocking dielectric in NAND memory strings'20169,230,979'High dielectric constant etch stop layer for a memory structure'20169,230,980'Single-semiconductor-layer channel in a memory opening for a three-dimensional non-volatile memory device'20169,230,973'Methods of fabricating a three-dimensional non-volatile memory device'20169,224,502'Techniques for detection and treating memory hole to local interconnect marginality defects'20159,209,031'Metal replacement process for low resistance source contacts in 3D NAND'20159,202,593'Techniques for detecting broken word lines in non-volatile memories'20159,177,966'Three dimensional NAND devices with air gap or low-k core'20159,123,714'Metal layer air gap formation'20159,099,496'Method of forming an active area with floating gate negative offset profile in FG NAND memory'20159,030,016'Semiconductor device with copper interconnects separated by air gaps'20159,023,719'High aspect ratio memory hole channel contact formation'20158,987,089'Methods of fabricating a three-dimensional non-volatile memory device'20158,946,023'Method of making a vertical NAND device using sequential etching of multilayer stacks'20158,778,749'Air isolation in high density non-volatile memory'20148,575,000'Copper interconnects separated by air gaps and method of making thereof'20138,530,297'Process for fabricating non-volatile storage'2013Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2013–2018Patents assigned to SANDISK TECHNOLOGIES INC (65)· patent assignee history
2013–2016Patents assigned to PACHAMUTHU JAYAVEL (4)· patent assignee history
2013–2014Patents assigned to PURAYATH VINOD R (3)· patent assignee history
2013–2014Patents assigned to MATAMIS GEORGE (2)· patent assignee history
2013–2016Based in Yokkaichi, JP· patent location history
2013Based in Mie-gun, JP· patent location history
2015–2021Based in San Jose, CA, US· patent location history
2015–2016Based in Milpitas, CA, US· patent location history
2015Based in Mie, JP· patent location history
2016–2021Patents assigned to SANDISK TECHNOLOGIES LLC (66)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SANDISK TECHNOLOGIES LLC | 66 | 2016–2021 |
| SANDISK TECHNOLOGIES INC | 65 | 2013–2018 |
| PACHAMUTHU JAYAVELself | 4 | 2013–2016 |
| PURAYATH VINOD R | 3 | 2013–2014 |
| MATAMIS GEORGE | 2 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 85 | 2015–2021 |
| Milpitas, California, US | 4 | 2015–2016 |
| Yokkaichi, JP | 3 | 2013–2016 |
| Mie, JP | 1 | 2015 |
| Mie-gun, JP | 1 | 2013 |