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Inventor

James S. Nakos

Inventor
Essex Junction, VT, US

Overview

63→
Patents
1993–2017
Patent span
Electricity
Primary field (CPC H)

Patents· 63 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices32%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
H10BElectronic memory devices10%
G06FElectric digital data processing4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
H01LSemiconductor devices3%
H01CResistors3%
H01JElectric discharge tubes or discharge lamps3%
C30BSingle-crystal growth2%
PatentTitleYear
9,646,125'Method for conversion of commercial microprocessor to radiation-hardened processor and resulting processor'20179,385,179'Deep trench decoupling capacitor and methods of forming'20169,269,787'Base profile of self-aligned bipolar transistors for power amplifier applications'20169,105,677'Base profile of self-aligned bipolar transistors for power amplifier applications'20158,872,281'Silicided trench contact to buried conductive layer'20148,796,044'Ferroelectric random access memory with optimized hardmask'20148,741,729'Dual contact trench resistor and capacitor in shallow trench isolation (STI) and methods of manufacture'20148,709,887'Method for fabricating a nitrided silicon-oxide gate dielectric'20148,658,435'Hydrogen barrier liner for ferro-electric random access memory (FRAM) chip'20148,614,137'Dual contact trench resistor in shallow trench isolation (STI) and methods of manufacture'20138,546,243'Dual contact trench resistor and capacitor in shallow trench isolation (STI) and methods of manufacture'20138,492,816'Deep trench decoupling capacitor'20138,450,168'Ferro-electric capacitor modules, methods of manufacture and design structures'20138,441,103'Embedded series deep trench capacitors and methods of manufacture'20138,395,196'Hydrogen barrier liner for ferro-electric random access memory (FRAM) chip'20138,384,140'Structure for dual contact trench capacitor and structure thereof'20138,338,265'Silicided trench contact to buried conductive layer'20128,284,017'Structure having substantially parallel resistor material lengths'20128,236,580'Copper contamination detection method and system for monitoring copper contamination'20128,198,663'Structure for dual contact trench capacitor and structure thereof'20128,143,135'Embedded series deep trench capacitors and methods of manufacture'20128,111,129'Resistor and design structure having substantially parallel resistor material lengths'20128,044,764'Resistor and design structure having resistor material length with sub-lithographic width'20118,012,848'Trench isolation and method of fabricating trench isolation'20117,957,917'Copper contamination detection method and system for monitoring copper contamination'20117,897,473'Method of manufacturing a dual contact trench capacitor'20117,897,939'Removable liners for charged particle beam systems'20117,897,940'Removable liners for charged particle beam systems'20117,888,142'Copper contamination detection method and system for monitoring copper contamination'20117,759,189'Method of manufacturing a dual contact trench capacitor'20107,759,260'Selective nitridation of gate oxides'20107,737,050'Method of fabricating a nitrided silicon oxide gate dielectric layer'20107,462,845'Removable liners for charged particle beam systems'20087,291,568'Method for fabricating a nitrided silicon-oxide gate dielectric'20077,138,691'Selective nitridation of gate oxides'20067,112,481'Method for forming self-aligned dual salicide in CMOS technologies'20067,067,368'Method for forming self-aligned dual salicide in CMOS technologies'20067,064,025'Method for forming self-aligned dual salicide in CMOS technologies'20067,045,372'Apparatus and method for forming a battery in an integrated circuit'20066,967,167'Silicon dioxide removing method'20056,909,157'Thermal nitrogen distribution method to improve uniformity of highly doped ultra-thin gate capacitors'20056,780,720'Method for fabricating a nitrided silicon-oxide gate dielectric'20046,706,644'Thermal nitrogen distribution method to improve uniformity of highly doped ultra-thin gate capacitors'20046,650,000'Apparatus and method for forming a battery in an integrated circuit'20036,522,304'Dual damascene horn antenna'20036,498,096'Borderless contact to diffusion with respect to gate conductor and methods for fabricating'20026,373,095'NVRAM cell having increased coupling ratio between a control gate and floating gate without an increase in cell area'20026,339,015'Method of fabricating a non-volatile semiconductor device'20026,256,755'Apparatus and method for detecting defective NVRAM cells'20016,232,633'NVRAM cell using sharp tip for tunnel erase'20016,221,704'Process for fabricating short channel field effect transistor with a highly conductive gate'20016,215,190'Borderless contact to diffusion with respect to gate conductor and methods for fabricating'20016,187,679'Low temperature formation of low resistivity titanium silicide'20016,054,745'Nonvolatile memory cell using microelectromechanical device'20006,022,770'NVRAM utilizing high voltage TFT device and method for making the same'20005,828,131'Low temperature formation of low resistivity titanium silicide'19985,691,549'Sidewall strap'19975,565,060'Methods and compositions for the selective etching of silicon'19965,521,118'Sidewall strap'19965,431,777'Methods and compositions for the selective etching of silicon'19955,268,330'Process for improving sheet resistance of an integrated circuit device gate'19935,226,732'Emissivity independent temperature measurement systems'19935,185,294'Boron out-diffused surface strap process'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2017Patents assigned to IBM (62)· patent assignee history
1993–2013Based in Essex, VT, US· patent location history
2000–2017Based in Essex Junction, VT, US· patent location history
2012–2014Patents assigned to NAKOS JAMES S (14)· patent assignee history
2012–2014Patents assigned to SHANK STEVEN M (7)· patent assignee history
2012–2013Patents assigned to KEMERER TIMOTHY W (6)· patent assignee history
2012–2014Patents assigned to COOLBAUGH DOUGLAS D (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM621993–2017
NAKOS JAMES Sself142012–2014
SHANK STEVEN M72012–2014
KEMERER TIMOTHY W62012–2013
COOLBAUGH DOUGLAS D22012–2014
Locations
LocationPatentsSpan
Essex Junction, VT, US422000–2017
Essex, VT, US211993–2013