Inventor

Larry D. Kinsman

Inventor

Boise, ID, US

Overview

1990–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 228 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1047%

H05KPrinted circuits14%

Y10TTechnical subjects covered by former us classification10%

H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation5%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%

Y02PClimate change mitigation technologies in the production or processing of goods2%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

G01RMeasuring electric variables2%

H01LSemiconductor devices2%

H01RElectrically-conductive connections2%

PatentTitleYear

10,770,492Chip scale package and related methods2020 10,767,460Method of chemically delaying peroxygen based viscosity reduction reactions2020 10,490,588Methods and apparatus for a thermal equalizer in an image sensor2019 10,388,684Image sensor packages formed using temporary protection layers and related methods2019 10,290,672Image sensor semiconductor packages and related methods2019 10,079,254Chip scale package and related methods2018 10,053,617Method of chemically increasing the efficiency of peroxygen based viscosity reduction reactions2018 9,947,705Image sensors with infrared-blocking layers2018 9,878,301'Method and composition for the remediation of contaminants'2018 9,771,782'Method of chemically delaying peroxygen based viscosity reduction reactions'2017 9,754,983'Chip scale package and related methods'2017 9,561,530'Method for the in situ remediation of contaminants'2017 8,981,511'Multi-chip package for imaging systems'2015 8,791,536'Stacked sensor packaging structure and method'2014 8,097,895'Electronic device package with an optical device'2012 7,969,810'256 Meg dynamic random access memory'2011 7,919,410'Packaging methods for imager devices'2011 7,871,859'Vertical surface mount assembly and methods'2011 7,829,991'Stackable ceramic FBGA for high thermal applications'2010 7,727,858'Method for fabricating a chip scale package using wafer level processing'2010 7,638,813'Methods of fabrication for flip-chip image sensor packages'2009 7,629,686'Bumped die and wire bonded board-on-chip package'2009 7,600,314'Methods for installing a plurality of circuit devices'2009 7,569,418'Methods for securing packaged semiconductor devices to carrier substrates'2009 7,541,658'Optically interactive device package array'2009 7,443,038'Flip-chip image sensor packages'2008 7,408,255'Assembly for stacked BGA packages'2008 7,400,032'Module assembly for stacked BGA packages'2008 7,396,702'Module assembly and method for stacked BGA packages'2008 7,385,298'Reduced-dimension microelectronic component assemblies with wire bonds and methods of making same'2008 7,384,805'Transfer mold semiconductor packaging processes'2008 7,321,455'Microelectronic devices and methods for packaging microelectronic devices'2008 7,285,442'Stackable ceramic FBGA for high thermal applications'2007 7,282,789'Back-to-back semiconductor device assemblies'2007 7,279,797'Module assembly and method for stacked BGA packages'2007 7,259,450'Double-packaged multi-chip semiconductor module'2007 7,227,261'Vertical surface mount assembly and methods'2007 7,214,566'Semiconductor device package and method'2007 7,183,191'Method for fabricating a chip scale package using wafer level processing'2007 7,151,013'Semiconductor package having exposed heat dissipating surface and method of fabrication'2006 7,148,083'Transfer mold semiconductor packaging processes'2006 7,125,749'Varied-thickness heat sink for integrated circuit (IC) packages and method of fabricating IC packages'2006 7,122,390'Methods of fabrication for flip-chip image sensor packages'2006 7,115,990'Bumped die and wire bonded board-on-chip package'2006 7,116,001'Bumped die and wire bonded board-on-chip package'2006 7,112,252'Assembly method for semiconductor die and lead frame'2006 7,095,122'Reduced-dimension microelectronic component assemblies with wire bonds and methods of making same'2006 7,095,115'Circuit substrates, semiconductor packages, and ball grid arrays'2006 7,091,622'Semiconductor device, ball grid array connection system, and method of making'2006 7,082,681'Methods for modifying a vertical surface mount package'2006 7,065,868'Methods for installing a circuit device'2006 7,057,291'Methods for securing vertically mountable semiconductor devices in back-to back relation'2006 7,015,063'Methods of utilizing a back to back semiconductor device module'2006 6,998,860'Method for burn-in testing semiconductor dice'2006 6,979,596'Method of fabricating a tape having apertures under a lead frame for conventional IC packages'2005 6,979,902'Chip size image sensor camera module'2005 6,974,725'Interconnections for a semiconductor device'2005 6,964,886'Methods of fabrication for flip-chip image sensor packages'2005 6,963,128'Vertically mountable and alignable semiconductor device assembly'2005 6,956,295'Flip-chip image sensor packages'2005 6,940,141'Flip-chip image sensor packages and methods of fabrication'2005 6,934,065'Microelectronic devices and methods for packaging microelectronic devices'2005 6,921,966'Tape under frame for lead frame IC package assembly'2005 6,911,737'Semiconductor device package and method'2005 6,906,424'Semiconductor package and method producing same'2005 6,903,465'Method and apparatus for a semiconductor package for vertical surface mounting'2005 6,900,079'Method for fabricating a chip scale package using wafer level processing'2005 6,894,372'Tape under frame for lead frame IC package assembly'2005 6,885,107'Flip-chip image sensor packages and methods of fabrication'2005 6,873,037'Vertical surface mount package utilizing a back-to-back semiconductor device module'2005 6,858,926'Stackable ceramic FBGA for high thermal applications'2005 6,838,768'Module assembly for stacked BGA packages'2005 6,833,612'Flip-chip image sensor packages'2004 6,828,173'Semiconductor device including edge bond pads and methods'2004 6,825,547'Semiconductor device including edge bond pads'2004 6,803,656'Semiconductor device including combed bond pad opening'2004 6,800,505'Semiconductor device including edge bond pads and related methods'2004 6,800,942'Vertically mountable semiconductor device and methods'2004 6,797,616'Circuit boards containing vias and methods for producing same'2004 6,798,063'Low profile ball grid array package'2004 6,781,839'Vertical surface mount apparatus with thermal carrier and method'2004 6,780,746'Method for fabricating a chip scale package using wafer level processing and devices resulting therefrom'2004 6,777,261'Method and apparatus for a semiconductor package for vertical surface mounting'2004 6,774,486'Circuit boards containing vias and methods for producing same'2004 6,773,965'Semiconductor device, ball grid array connection system, and method of making'2004 6,765,803'Semiconductor device socket'2004 6,760,224'Heat sink with alignment and retaining features'2004 6,744,137'Bumped die and wire bonded board-on-chip package'2004 6,737,734'Structure and method for securing bussing leads'2004 6,735,102'256 Meg dynamic random access memory'2004 6,734,529'Vertically mountable interposer and assembly'2004 6,730,994'Interdigitated capacitor design for integrated circuit lead frames and methods'2004 6,717,245'Chip scale packages performed by wafer level processing'2004 6,709,893'Interconnections for a semiconductor device and method for forming same'2004 6,699,734'Method and apparatus for coupling a semiconductor die to die terminals'2004 6,700,206'Stacked semiconductor package and method producing same'2004 6,684,493'Vertically mountable interposer, assembly and method'2004 6,681,480'Method and apparatus for installing a circuit device'2004 6,682,998'Methods for bumped die and wire bonded board-on-chip package'2004 6,669,738'Low profile semiconductor package'2003 6,650,007'Stackable ceramic fbga for high thermal applications'2003 6,635,954'Stress reduction feature for LOC lead frame'2003 6,634,098'Methods for assembling, modifying and manufacturing a vertical surface mount package'2003 6,628,136'Method and apparatus for testing a semiconductor package'2003 6,611,058'Vertical surface mount assembly and methods'2003 6,610,162'Methods for stress reduction feature for LOC lead frame'2003 6,607,943'Low profile ball grid array package'2003 6,600,215'Method and apparatus for coupling a semiconductor die to die terminals'2003 6,590,277'Reduced stress LOC assembly'2003 6,579,746'Method and apparatus for coupling a semiconductor die to die terminals'2003 6,577,503'Vertical surface mount apparatus with thermal carrier'2003 6,563,712'Heak sink chip package'2003 6,563,217'Module assembly for stacked BGA packages'2003 6,558,966'Apparatus and methods of packaging and testing die'2003 6,555,399'Double-packaged multichip semiconductor module'2003 6,545,343'Hybrid frame with lead-lock tape'2003 6,541,856'Thermally enhanced high density semiconductor package'2003 6,534,339'Semiconductor device comprising a socket and method for forming same'2003 6,531,765'Interdigitated capacitor design for integrated circuit lead frames and method'2003 6,531,764'Vertically mountable semiconductor device, assembly, and methods'2003 6,528,408'Method for bumped die and wire bonded board-on-chip package'2003 6,525,943'Heat sink with alignment and retaining features'2003 6,518,650'Tape under frame for lead frame IC package assembly'2003 6,512,290'Vertically mountable and alignable semiconductor device, assembly, and methods'2003 6,512,302'Apparatus and methods of packaging and testing die'2003 6,511,863'Method and apparatus for a semiconductor package for vertical surface mounting'2003 6,507,109'Vertical surface mount package utilizing a back-to-back semiconductor device module'2003 6,506,629'Varied-thickness heat sink for integrated circuit (IC) packages and method of fabricating IC packages'2003 6,495,400'Method of forming low profile semiconductor package'2002 6,492,728'Vertical surface mount assembly'2002 6,493,229'Heat sink chip package'2002 6,482,674'Semiconductor package having metal foil die mounting plate'2002 6,477,073'256 meg dynamic random access memory'2002 6,455,351'Vertical surface mount assembly and methods'2002 6,442,044'Semiconductor device socket, assembly and methods'2002 6,437,435'Vertically mountable interposer, assembly and method'2002 6,426,875'Heat sink chip package'2002 6,417,024'Back-to-back semiconductor device module, assemblies including the same and methods'2002 6,418,023'Vertical surface mount apparatus with thermal carrier'2002 6,414,391'Module assembly for stacked BGA packages with a common bus bar in the assembly'2002 6,414,374'Semiconductor device including edge bond pads and methods'2002 6,408,509'Vertically mountable interposer, assembly and method'2002 6,410,406'Semiconductor device including edge bond pads and methods'2002 6,396,134'Interdigitated capacitor design for integrated circuit lead frames'2002 6,396,131'Stress reduction feature for LOC lead frame'2002 6,383,839'Vertically mountable semiconductor device and methods'2002 6,380,631'Apparatus and methods of packaging and testing die'2002 6,380,630'Vertical surface mount package utilizing a back-to-back semiconductor device module'2002 6,372,552'Semiconductor device, ball grid array connection system, and method of making'2002 6,365,437'Method of connecting a die in an integrated circuit module'2002 6,342,731'Vertically mountable semiconductor device, assembly, and methods'2002 6,329,709'Interconnections for a semiconductor device'2001 6,330,159'Vertical surface mount apparatus with thermal carrier'2001 6,320,253'Semiconductor device comprising a socket and method for forming same'2001 6,314,011'256 Meg dynamic random access memory'2001 6,306,687'Tape under frame for conventional-type IC package assembly'2001 6,297,960'Heat sink with alignment and retaining features'2001 6,297,548'Stackable ceramic FBGA for high thermal applications'2001 6,297,542'Connecting a die in an integrated circuit module'2001 6,295,209'Semiconductor device including combed bond pad opening, assemblies and methods'2001 6,294,839'Apparatus and methods of packaging and testing die'2001 6,291,894'Method and apparatus for a semiconductor package for vertical surface mounting'2001 6,277,225'Stress reduction feature for LOC lead frame'2001 6,268,650'Semiconductor device, ball grid array connection system, and method of making'2001 6,268,655'Semiconductor device including edge bond pads and methods'2001 6,265,764'Interdigitated capacitor design for integrated circuit lead frames'2001 6,265,773'Vertically mountable and alignable semiconductor device, assembly, and methods'2001 6,251,708'Hybrid frame with lead-lock tape'2001 6,246,110'Downset lead frame for semiconductor packages'2001 6,239,012'Vertically mountable semiconductor device and methods'2001 6,235,551'Semiconductor device including edge bond pads and methods'2001 6,232,146'Semiconductor device including combed bond pad opening, assemblies and methods'2001 6,228,677'Vertical surface mount assembly and methods'2001 6,215,175'Semiconductor package having metal foil die mounting plate'2001 6,215,183'Vertical surface mount assembly and methods'2001 6,215,177'Tape under frame for conventional-type IC package assembly'2001 6,198,636'Semiconductor device socket, assembly and methods'2001 6,191,474'Vertically mountable interposer assembly and method'2001 6,172,419'Low profile ball grid array package'2001 6,159,764'Varied-thickness heat sink for integrated circuit (IC) packages and method of fabricating IC packages'2000 6,153,924'Multilayered lead frame for semiconductor package'2000 6,147,411'Vertical surface mount package utilizing a back-to-back semiconductor device module'2000 6,146,922'Hybrid frame with lead-lock tape'2000 6,143,589'Tape under frame for conventional-type IC package assembly'2000 6,144,560'Semiconductor device including combed bond pad opening, assemblies and methods'2000 6,140,696'Vertically mountable semiconductor device and methods'2000 6,133,068'Increasing the gap between a lead frame and a semiconductor die'2000 6,134,111'Vertical surface mount apparatus with thermal carrier'2000 6,121,673'Leadframe finger support'2000 6,122,171'Heat sink chip package and method of making'2000 6,114,770'Low profile semiconductor package'2000 6,114,756'Interdigitated capacitor design for integrated circuit leadframes'2000 6,115,254'Vertical surface mount apparatus with thermal carrier'2000 6,095,822'Component module holder'2000 6,091,251'Discrete die burn-in for nonpackaged die'2000 6,091,250'Discrete die burn-in for nonpackaged die'2000 6,091,133'Assembly of a semiconductor device and paddleless lead frame having tape extending between the lead fingers'2000 6,091,606'Semiconductor device including combed bond pad opening, assemblies and methods'2000 6,088,237'Semiconductor device socket, assembly and methods'2000 6,087,723'Vertical surface mount assembly and methods'2000 6,088,238'Semiconductor device socket, assembly and methods'2000 6,083,777'Reduced stress LOC assembly'2000 6,075,283'Downset lead frame for semiconductor packages'2000 6,063,650'Reduced stress LOC assembly'2000 6,008,531'Hybrid frame with lead-lock tape'1999 6,005,286'Increasing the gap between a lead frame and a semiconductor die'1999 6,002,165'Multilayered lead frame for semiconductor packages'1999 5,997,378'Method for evacuating and sealing field emission displays'1999 5,995,378'Semiconductor device socket, assembly and methods'1999 5,940,277'Semiconductor device including combed bond pad opening, assemblies and methods'1999 5,930,602'Leadframe finger support'1999 5,915,166'Tape under frame for conventional-type IC package assembly'1999 5,897,340'Hybrid frame with lead-lock tape'1999 5,872,398'Reduced stress LOC assembly including cantilevered leads'1999 5,788,551'Field emission display package and method of fabrication'1998 5,789,803'Semiconductor package'1998 5,729,049'Tape under frame for conventional-type IC package assembly'1998 5,717,246'Hybrid frame with lead-lock tape'1998 5,697,825'Method for evacuating and sealing field emission displays'1997 5,696,033'Method for packaging a semiconductor die'1997 5,375,320'Method of forming \"J\" leads on a semiconductor device'1994 5,342,807'Soft bond for semiconductor dies'1994 5,336,649'Removable adhesives for attachment of semiconductor dies'1994 5,302,891'Discrete die burn-in for non-packaged die'1994 5,173,451'Soft bond for semiconductor dies'1992 5,155,067'Packaging for a semiconductor die'1992 5,107,328'Packaging means for a semiconductor die having particular shelf structure'1992 4,914,269'Method of sealing a ceramic lid on a ceramic semiconductor package with a high-power laser'1990

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1990–2010Patents assigned to MICRON TECHNOLOGY INC (205)· patent assignee history

1990–2020Based in Boise, ID, US· patent location history

2004–2012Based in Kuna, ID, US· patent location history

2011–2012Patents assigned to ROUND ROCK RES LLC (3)· patent assignee history

2011–2014Patents assigned to APTINA IMAGING CORP (2)· patent assignee history

2017–2020Patents assigned to SEMICONDUCTOR COMPONENTS IND LLC (7)· patent assignee history

2017–2020Patents assigned to ORIN TECH LLC (5)· patent assignee history

2017–2020Based in Verona, WI, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	205	1990–2010
SEMICONDUCTOR COMPONENTS IND LLC	7	2017–2020
ORIN TECH LLC	5	2017–2020
ROUND ROCK RES LLC	3	2011–2012
APTINA IMAGING CORP	2	2011–2014

Locations

Location	Patents	Span
Boise, ID, US	207	1990–2020
Kuna, ID, US	16	2004–2012
Verona, WI, US	5	2017–2020