Inventor
Eric C. Fromm
Inventor
Eau Claire, WI, US
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing59%
H04LTransmission of digital information, e.g. telegraphic communication25%
G11CStatic stores6%
F02BInternal-combustion piston engines3%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes3%
H04JMultiplex communication3%
PatentTitleYear
10,944,694Predictive arbitration circuit202110,721,185Age-based arbitration circuit202010,592,465Node controller direct socket group memory access202010,521,260Workload management system and process20199,250,826'Enhanced performance monitoring method and apparatus'20169,237,093'Bandwidth on-demand adaptive routing'20169,208,090'Transactional memory proxy'20159,104,343'Global synchronous clock circuit and method for blade processors'20158,239,566'Non-saturating fairness protocol and method for NACKing systems'20127,587,305'Transistor level verilog'20096,925,547'Remote address translation in a multiprocessor system'20056,839,856'Method and circuit for reliable data capture in the presence of bus-master changeovers'20056,779,072'Method and apparatus for accessing MMR registers distributed across a large asic'20046,604,185'Distribution of address-translation-purge requests to multiple processors'20036,119,198'Recursive address centrifuge for distributed memory massively parallel processing systems'20006,029,212'Method of handling arbitrary size message queues in which a message is written into an aligned block of external registers within a plurality of external registers'20005,835,925'Using external registers to extend memory reference capabilities of a microprocessor'19985,784,706'Virtual to logical to physical address translation for distributed memory massively parallel processing systems'19985,765,181'System and method of addressing distributed memory within a massively parallel processing system'19985,696,922'Recursive address centrifuge for distributed memory massively parallel processing systems'19975,592,487'Communication protocol for transferring information across a serial communication link'19975,581,705'Messaging facility with hardware tail pointer and software implemented head pointer message queue for distributed memory massively parallel processing system'19965,434,995'Barrier synchronization for distributed memory massively parallel processing systems'19955,420,583'Fiber optic channel extender interface method and apparatus'19955,390,041'Fiber optic channel extender interface method and apparatus'19955,321,697'Solid state storage device'19944,951,246'Nibble-mode dram solid state storage device'19904,771,440'Data modulation interface'1988Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1988–2000Patents assigned to CRAY RESEARCH INC (14)· patent assignee history
1988–2021Based in Eau Claire, WI, US· patent location history
2003–2005Patents assigned to SILICON GRAPHICS INC (4)· patent assignee history
2009Patents assigned to CRAY INC (1)· patent assignee history
2015–2016Patents assigned to SILICON GRAPHICS INT CORP (4)· patent assignee history
2019–2021Patents assigned to HEWLETT PACKARD ENTPR DEV LP (4)· patent assignee history
2020Based in Chippewa Falls, WI, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CRAY RESEARCH INC | 14 | 1988–2000 |
| HEWLETT PACKARD ENTPR DEV LP | 4 | 2019–2021 |
| SILICON GRAPHICS INC | 4 | 2003–2005 |
| SILICON GRAPHICS INT CORP | 4 | 2015–2016 |
| CRAY INC | 1 | 2009 |
Locations
| Location | Patents | Span |
|---|---|---|
| Eau Claire, WI, US | 27 | 1988–2021 |
| Chippewa Falls, WI, US | 1 | 2020 |