Inventor

Sanaz K. Gardner

Inventor

Portland, OR, US

Overview

2014–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 64 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary

H01LSemiconductor devices31%

H10DInorganic electric semiconductor devices30%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%

B82YSpecific uses or applications of nanostructures3%

H10BElectronic memory devices1%

H10HInorganic light-emitting semiconductor devices having potential barriers1%

H10NElectric solid-state devices not otherwise provided for1%

B81BMicrostructural devices or systems, e.g. micromechanical devices1%

B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems1%

PatentTitleYear

11,114,556Gate stack design for GaN e-mode transistor performance2021 11,056,532Techniques for monolithic co-integration of polycrystalline thin-film bulk acoustic resonator devices and monocrystalline III-N semiconductor transistor devices2021 11,031,305Laterally adjacent and diverse group III-N transistors2021 11,004,982Gate for a transistor2021 10,998,260Microelectronic devices having air gap structures integrated with interconnect for reduced parasitic capacitances2021 10,930,500Wurtzite heteroepitaxial structures with inclined sidewall facets for defect propagation control in silicon CMOS-compatible semiconductor devices2021 10,930,766Ge NANO wire transistor with GAAS as the sacrificial layer2021 10,903,364Semiconductor device with released source and drain2021 10,850,977Group III-N MEMS structures on a group IV substrate2020 10,847,653Semiconductor device having metallic source and drain regions2020 10,840,352Nanowire transistors with embedded dielectric spacers2020 10,804,359Geometric manipulation of 2DEG region in source/drain extension of GaN transistor2020 10,804,386Gate stack design for GaN e-mode transistor performance2020 10,784,352Method to achieve a uniform Group IV material layer in an aspect ratio trapping trench2020 10,756,183N-channel gallium nitride transistors2020 10,665,577Co-integrated III-N voltage regulator and RF power amplifier for envelope tracking systems2020 10,665,708Semiconductor devices with raised doped crystalline structures2020 10,644,137III-V finfet transistor with V-groove S/D profile for improved access resistance2020 10,622,448Transistors including retracted raised source/drain to reduce parasitic capacitances2020 10,593,785Transistors having ultra thin fin profiles and their methods of fabrication2020 10,580,895Wide band gap transistors on non-native semiconductor substrates2020 10,574,187Envelope-tracking control techniques for highly-efficient RF power amplifiers2020 10,553,689Multiple stacked field-plated GaN transistor and interlayer dielectrics to improve breakdown voltage and reduce parasitic capacitances2020 10,546,927Self-aligned transistor structures enabling ultra-short channel lengths2020 10,475,888Integration of III-V devices on Si wafers2019 10,431,690High electron mobility transistors with localized sub-fin isolation2019 10,388,777Heteroepitaxial structures with high temperature stable substrate interface material2019 10,347,544Co-planar p-channel and n-channel gallium nitride-based transistors on silicon and techniques for forming same2019 10,325,774Wurtzite heteroepitaxial structures with inclined sidewall facets for defect propagation control in silicon CMOS-compatible semiconductor devices2019 10,249,742Offstate parasitic leakage reduction for tunneling field effect transistors2019 10,249,740Ge nano wire transistor with GaAs as the sacrificial layer2019 10,243,069Gallium nitride transistor having a source/drain structure including a single-crystal portion abutting a 2D electron gas2019 10,229,991III-N epitaxial device structures on free standing silicon mesas2019 10,217,673Integrated circuit die having reduced defect group III-nitride structures and methods associated therewith2019 10,211,327Semiconductor devices with raised doped crystalline structures2019 10,204,989Method of fabricating semiconductor structures on dissimilar substrates2019 10,096,682III-N devices in Si trenches2018 10,096,474Methods and structures to prevent sidewall defects during selective epitaxy2018 10,096,683Group III-N transistor on nanoscale template structures2018 10,084,043High mobility nanowire fin channel on silicon substrate formed using sacrificial sub-fin2018 10,056,456N-channel gallium nitride transistors2018 10,032,911Wide band gap transistor on non-native semiconductor substrate2018 9,923,087'Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation'2018 9,922,826'Integrated circuit die having reduced defect group III-nitride layer and methods associated therewith'2018 9,847,432Forming III-V device structures on (111) planes of silicon fins2017 9,847,448Forming LED structures on silicon fins2017 9,837,499Self-aligned gate last III-N transistors2017 9,806,203'Nonplanar III-N transistors with compositionally graded semiconductor channels'2017 9,716,149'Group III-N transistors on nanoscale template structures'2017 9,698,222'Method of fabricating semiconductor structures on dissimilar substrates'2017 9,698,013'Methods and structures to prevent sidewall defects during selective epitaxy'2017 9,673,045'Integration of III-V devices on Si wafers'2017 9,660,085'Wide band gap transistors on non-native semiconductor substrates and methods of manufacture thereof'2017 9,660,064'Low sheet resistance GaN channel on Si substrates using InAlN and AlGaN bi-layer capping stack'2017 9,640,422'III-N devices in Si trenches'2017 9,590,069'Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation'2017 9,373,693'Nonplanar III-N transistors with compositionally graded semiconductor channels'2016 9,362,369'Group III-N transistors on nanoscale template structures'2016 9,219,079'Group III-N transistor on nanoscale template structures'2015 8,954,021'Group III-N transistors on nanoscale template structures'2015 8,896,101'Nonplanar III-N transistors with compositionally graded semiconductor channels'2014 8,785,909'Non-planar semiconductor device having channel region with low band-gap cladding layer'2014 8,785,907'Epitaxial film growth on patterned substrate'2014 8,768,271'Group III-N transistors on nanoscale template structures'2014

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2014–2021Patents assigned to INTEL CORP (64)· patent assignee history

2014–2015Patents assigned to CHAU ROBERT S (5)· patent assignee history

2014–2015Patents assigned to CHU-KUNG BENJAMIN (5)· patent assignee history

2014–2015Patents assigned to RADOSAVLJEVIC MARKO (5)· patent assignee history

2014–2015Patents assigned to DASGUPTA SANSAPTAK (4)· patent assignee history

2014–2021Based in Portland, OR, US· patent location history

2014–2021Based in Hillsboro, OR, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	64	2014–2021
CHAU ROBERT S	5	2014–2015
CHU-KUNG BENJAMIN	5	2014–2015
RADOSAVLJEVIC MARKO	5	2014–2015
DASGUPTA SANSAPTAK	4	2014–2015

Locations

Location	Patents	Span
Portland, OR, US	36	2014–2021
Hillsboro, OR, US	28	2014–2021