Inventor

Wuu Yean Tay

Inventor

Singapore, SG

Overview

2002–2017

Patent span

Electricity

Primary field (CPC H)

Patents· 28 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1030%

H05KPrinted circuits18%

G01RMeasuring electric variables17%

Y02PClimate change mitigation technologies in the production or processing of goods15%

H10DInorganic electric semiconductor devices6%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%

B33YAdditive manufacturing, i.e. manufacturing of three-dimensional [3d] objects by additive deposition, additive agglomeration or additive layering, e.g. by 3d printing, stereolithography or selective laser sintering5%

H01LSemiconductor devices1%

Y10TTechnical subjects covered by former us classification1%

PatentTitleYear

9,721,874'Pre-encapsulated lead frames for microelectronic device packages, and associated methods'2017 8,525,320'Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods'2013 8,357,566'Pre-encapsulated lead frames for microelectronic device packages, and associated methods'2013 7,915,718'Apparatus for flip-chip packaging providing testing capability'2011 7,820,459'Methods relating to the reconstruction of semiconductor wafers for wafer level processing including forming of alignment protrusion and removal of alignment material'2010 7,754,531'Method for packaging microelectronic devices'2010 7,573,006'Apparatus relating to the reconstruction of semiconductor wafers for wafer-level processing'2009 7,425,462'Methods relating to the reconstruction of semiconductor wafers for wafer-level processing'2008 7,368,391'Methods for designing carrier substrates with raised terminals'2008 7,285,971'Integrated circuit (IC) test assembly including phase change material for stabilizing temperature during stress testing of integrated circuits and method thereof'2007 7,190,074'Reconstructed semiconductor wafers including alignment droplets contacting alignment vias'2007 7,116,122'Method for ball grid array chip packages having improved testing and stacking characteristics'2006 7,071,012'Methods relating to the reconstruction of semiconductor wafers for wafer-level processing'2006 7,061,124'Solder masks including dams for at least partially surrounding terminals of a carrier substrate and recessed areas positioned adjacent to the dams, and carrier substrates including such solder masks'2006 7,030,640'Integrated circuit (IC) test assembly including phase change material for stabilizing temperature during stress testing of integrated circuits and method thereof'2006 7,018,871'Solder masks for use on carrier substrates, carrier substrates and semiconductor device assemblies including such solder masks, and methods'2006 6,856,155'Methods and apparatus for testing and burn-in of semiconductor devices'2005 6,847,220'Method for ball grid array chip packages having improved testing and stacking characteristics'2005 6,787,923'Solder masks for use on carrier substrates, carrier substrates and semiconductor device assemblies including such solder masks'2004 6,740,984'Ball grid array chip packages having improved testing and stacking characteristics'2004 6,740,983'Method for ball grind array chip packages having improved testing and stacking characteristics'2004 6,693,363'Ball grid array chip packages having improved testing and stacking characteristics'2004 6,674,175'Ball grid array chip packages having improved testing and stacking characteristics'2004 6,600,335'Method for ball grid array chip packages having improved testing and stacking characteristics'2003 6,522,018'Ball grid array chip packages having improved testing and stacking characteristics'2003 6,522,019'Ball grid array chip packages having improved testing and stacking characteristics'2003 6,448,664'Ball grid array chip packages having improved testing and stacking characteristics'2002 6,420,789'Ball grid array chip packages having improved testing and stacking characteristics'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2017Patents assigned to MICRON TECHNOLOGY INC (28)· patent assignee history

2002–2017Based in Singapore, SG· patent location history

2013Patents assigned to TAY WUU YEAN (2)· patent assignee history

2013Patents assigned to BOON SUAN JEUNG (1)· patent assignee history

2013Patents assigned to CHIA YONG POO (1)· patent assignee history

2013Patents assigned to CHONG CHIN HUI (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	28	2002–2017
TAY WUU YEANself	2	2013
BOON SUAN JEUNG	1	2013
CHIA YONG POO	1	2013
CHONG CHIN HUI	1	2013

Locations

Location	Patents	Span
Singapore, SG	28	2002–2017