Inventor
Tien-Jen Cheng
Inventor
Bedford, NY, US
Overview
Patents· 34 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1036%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
H05KPrinted circuits9%
H01LSemiconductor devices8%
C25DProcesses for the electrolytic or electrophoretic production of coatings6%
Y02PClimate change mitigation technologies in the production or processing of goods6%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
C23CCoating metallic material4%
H10DInorganic electric semiconductor devices4%
B08BCleaning in general3%
PatentTitleYear
9,673,176'Metal to metal bonding for stacked (3D) integrated circuits'20179,666,563'Metal to metal bonding for stacked (3D) integrated circuits'20179,653,431'Metal to metal bonding for stacked (3D) integrated circuits'20179,653,432'Metal to metal bonding for stacked (3D) integrated circuits'20179,515,051'Metal to metal bonding for stacked (3D) integrated circuits'20169,017,486'Deposition chamber cleaning method including stressed cleaning layer'20159,017,487'Deposition chamber cleaning method including stressed cleaning layer'20158,916,448'Metal to metal bonding for stacked (3D) integrated circuits'20148,444,868'Method for removing copper oxide layer'20138,415,252'Selective copper encapsulation layer deposition'20138,384,219'Semiconductor having interconnects with improved mechanical properties by insertion of nanoparticles'20138,373,273'Methods of forming integrated circuit devices having damascene interconnects therein with metal diffusion barrier layers and devices formed thereby'20138,232,200'Methods of forming integrated circuit devices having damascene interconnects therein with metal diffusion barrier layers and devices formed thereby'20128,129,269'Method of improving mechanical properties of semiconductor interconnects with nanoparticles'20128,105,937'Conformal adhesion promoter liner for metal interconnects'20128,026,166'Interconnect structures comprising capping layers with low dielectric constants and methods of making the same'20117,923,836'BLM structure for application to copper pad'20117,767,575'Forming robust solder interconnect structures by reducing effects of seed layer underetching'20107,572,726'Method of forming a bond pad on an I/C chip and resulting structure'20097,566,649'Compressible films surrounding solder connectors'20097,473,997'Method for forming robust solder interconnect structures by reducing effects of seed layer underetching'20097,332,821'Compressible films surrounding solder connectors'20087,144,490'Method for selective electroplating of semiconductor device I/O pads using a titanium-tungsten seed layer'20066,995,475'I/C chip suitable for wire bonding'20066,995,084'Method for forming robust solder interconnect structures by reducing effects of seed layer underetching'20066,992,389'Barrier for interconnect and method'20066,927,472'Fuse structure and method to form the same'20056,924,185'Fuse structure and method to form the same'20056,896,784'Method for controlling local current to achieve uniform plating thickness'20056,890,413'Method and apparatus for controlling local current to achieve uniform plating thickness'20056,534,863'Common ball-limiting metallurgy for I/O sites'20036,235,412'Corrosion-resistant terminal metal pads for thin film packages'20016,083,375'Process for producing corrosion-resistant terminal metal pads for thin film packages'20005,728,433'Method for gold replenishment of electroless gold bath'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2017Based in Bedford, NY, US· patent location history
2000–2017Patents assigned to IBM (31)· patent assignee history
2010Based in Beford, NY, US· patent location history
2011–2013Patents assigned to SAMSUNG ELECTRONICS CO LTD (3)· patent assignee history
2012–2015Patents assigned to CHENG TIEN-JEN (6)· patent assignee history
2012–2015Patents assigned to LI ZHENGWEN (4)· patent assignee history
2012–2013Patents assigned to ZHU HUILONG (3)· patent assignee history
2013Based in Hopewell Junction, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 31 | 2000–2017 |
| CHENG TIEN-JENself | 6 | 2012–2015 |
| LI ZHENGWEN | 4 | 2012–2015 |
| SAMSUNG ELECTRONICS CO LTD | 3 | 2011–2013 |
| ZHU HUILONG | 3 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Bedford, New York, US | 31 | 1998–2017 |
| Hopewell Junction, New York, US | 2 | 2013 |
| Beford, New York, US | 1 | 2010 |