Inventor
Jean-Marc Dortu
Inventor
Munich, DE
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores48%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses19%
H03KPulse technique11%
G06FElectric digital data processing7%
B02CCrushing, pulverising, or disintegrating in general4%
H04LTransmission of digital information, e.g. telegraphic communication4%
H10DInorganic electric semiconductor devices4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
PatentTitleYear
8,635,393'Semiconductor memory having a short effective word line cycle time and method for reading data from a semiconductor memory of this type'20147,499,371'Semiconductor memory system with a variable and settable preamble f'20097,467,254'Semiconductor memory device with write protected memory banks'20087,092,300'Memory apparatus having a short word line cycle time and method for operating a memory apparatus'20067,047,371'Integrated memory having a memory cell array containing a plurality of memory banks, and circuit configuration having an integrated memory'20067,009,902'Semiconductor memory having a first and second sense amplifier for sensing a memory cell voltage during a normal mode and a refresh mode'20066,922,764'Memory, processor system and method for performing write operations on a memory region'20056,791,358'Circuit configuration with signal lines for serially transmitting a plurality of bit groups'20046,781,220'Printed circuit board for semiconductor memory device'20046,707,705'Integrated dynamic memory device and method for operating an integrated dynamic memory'20046,646,908'Integrated memory chip with a dynamic memory'20036,628,553'Data output interface, in particular for semiconductor memories'20036,252,443'Delay element using a delay locked loop'20016,229,364'Frequency range trimming for a delay line'20016,127,866'Delay-locked-loop (DLL) having symmetrical rising and falling clock edge type delays'20006,100,733'Clock latency compensation circuit for DDR timing'20006,043,694'Lock arrangement for a calibrated DLL in DDR SDRAM applications'20005,978,931'Variable domain redundancy replacement configuration for a memory device'19995,881,003'Method of making a memory device fault tolerant using a variable domain redundancy replacement configuration'19994,965,464'Power amplifier circuit for integrated digital circuits'19904,958,319'Address amplifier circuit having automatic interlock and protection against multiple addressing for use in static GaAs RAMs'19904,612,560'Field effect transistor operating in the enhancement mode'1986Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1990–2000Patents assigned to SIEMENS AG (6)· patent assignee history
1990–2008Based in Munich, DE· patent location history
1999–2001Patents assigned to IBM (5)· patent assignee history
1999–2000Based in South Burlington, VT, US· patent location history
2000–2001Patents assigned to INFINEON TECHNOLOGIES CORP (3)· patent assignee history
2003–2009Patents assigned to INFINEON TECHNOLOGIES AG (11)· patent assignee history
2003–2004Based in Mnchen, DE· patent location history
2005–2006Based in München, DE· patent location history
2009–2014Based in Tokyo, JP· patent location history
2014Patents assigned to DORTU JEAN-MARC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INFINEON TECHNOLOGIES AG | 11 | 2003–2009 |
| SIEMENS AG | 6 | 1990–2000 |
| IBM | 5 | 1999–2001 |
| INFINEON TECHNOLOGIES CORP | 3 | 2000–2001 |
| DORTU JEAN-MARCself | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Munich, DE | 7 | 1990–2008 |
| München, DE | 4 | 2005–2006 |
| Mnchen, DE | 4 | 2003–2004 |
| South Burlington, VT, US | 4 | 1999–2000 |
| Tokyo, JP | 2 | 2009–2014 |