Inventor
Cornelius A. van der Jeugd
Inventor
Heverlee, BE
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1040%
C23CCoating metallic material33%
H10DInorganic electric semiconductor devices10%
H01LSemiconductor devices9%
B01JChemical or physical processes, e.g. catalysis or colloid chemistry3%
C01BNon-metallic elements2%
C30BSingle-crystal growth2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
PatentTitleYear
10,343,907Method and system for delivering hydrogen peroxide to a semiconductor processing chamber20199,837,271Process for forming silicon-filled openings with a reduced occurrence of voids20179,552,979'Cyclic aluminum nitride deposition in a batch reactor'20179,443,730'Process for forming silicon-filled openings with a reduced occurrence of voids'20169,431,238'Reactive curing process for semiconductor substrates'20167,691,750'Methods of forming films in semiconductor devices with solid state reactants'20107,655,093'Wafer support system'20107,645,486'Method of manufacturing a silicon dioxide layer'20107,629,270'Remote plasma activated nitridation'20097,294,582'Low temperature silicon compound deposition'20077,186,298'Wafer support system'20077,153,772'Methods of forming silicide films in semiconductor devices'20066,692,576'Wafer support system'20046,491,757'Wafer support system'20026,464,792'Process chamber with downstream getter plate'20026,454,866'Wafer support system'20026,343,183'Wafer support system'20026,335,280'Tungsten silicide deposition process'20026,203,622'Wafer support system'20016,126,744'Method and system for adjusting semiconductor processing equipment'20006,113,702'Wafer support system'20006,093,252'Process chamber with inner support'20006,086,680'Low-mass susceptor'20006,053,982'Wafer support system'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2010Patents assigned to ASM INC (15)· patent assignee history
2000–2010Based in Portland, OR, US· patent location history
2000–2002Based in Tempe, AZ, US· patent location history
2006–2010Patents assigned to ASM INT (4)· patent assignee history
2006–2019Based in Heverlee, BE· patent location history
2010Patents assigned to SOITEC SILICON ON INSULATOR (1)· patent assignee history
2016–2019Patents assigned to ASM IP HOLDING BV (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ASM INC | 15 | 2000–2010 |
| ASM IP HOLDING BV | 5 | 2016–2019 |
| ASM INT | 4 | 2006–2010 |
| SOITEC SILICON ON INSULATOR | 1 | 2010 |
Locations
| Location | Patents | Span |
|---|---|---|
| Heverlee, BE | 10 | 2006–2019 |
| Portland, OR, US | 8 | 2000–2010 |
| Tempe, AZ, US | 6 | 2000–2002 |