Inventor
Takeru Matsuoka
Inventor
Tokyo, JP
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices28%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1023%
H01LSemiconductor devices19%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
C23CCoating metallic material4%
H03KPulse technique2%
H10BElectronic memory devices2%
PatentTitleYear
11,094,532Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium202111,056,337Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium202111,004,931Semiconductor device202110,978,588Semiconductor device202110,020,391Semiconductor device and manufacturing method of the same20189,401,398'Semiconductor device including transistor'20169,111,771'Semiconductor device'20158,884,362'Semiconductor device and manufacturing method of the same'20148,872,257'Semiconductor device'20148,350,322'Semiconductor device and method for manufacturing the same'20136,888,258'Semiconductor device including copper interconnect line and bonding pad, and method of manufacturing the same'20056,740,564'Method for manufacturing a semiconductor device'20046,696,732'Semiconductor device having S/D to S/D connection and isolation region between two semiconductor elements'20046,683,000'Semiconductor-device fabrication method'20046,586,838'Semiconductor device'20036,573,603'Semiconductor device, and method of manufacturing the same'20036,555,887'Semiconductor device with multi-layer interconnection'20036,503,836'Method and apparatus for manufacturing semiconductor device'20036,483,140'DRAM storage node with insulating sidewalls'20026,479,356'Method of manufacturing a semiconductive device with an enhanced junction breakdown strength'20026,417,575'Semiconductor device and fabrication process therefor'20026,081,007'Semiconductor device comprising MIS transistor with high concentration channel injection region'20005,018,168'Clock signal conversion circuit'1991Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2004Patents assigned to MITSUBISHI ELECTRIC CORP (10)· patent assignee history
2000–2005Based in Tokyo, JP· patent location history
2002–2016Based in Hyogo, JP· patent location history
2004–2005Patents assigned to RENESAS TECH CORP (2)· patent assignee history
2013–2021Patents assigned to TOSHIBA KK (8)· patent assignee history
2013–2014Patents assigned to MATSUOKA TAKERU (2)· patent assignee history
2018–2021Based in Himeji, JP· patent location history
2021Patents assigned to KOKUSAI ELECTRIC CORP (2)· patent assignee history
2021Based in Toyama-shi, JP· patent location history
2021Based in Ishikawa-gun, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MITSUBISHI ELECTRIC CORP | 10 | 2000–2004 |
| TOSHIBA KK | 8 | 2013–2021 |
| KOKUSAI ELECTRIC CORP | 2 | 2021 |
| MATSUOKA TAKERUself | 2 | 2013–2014 |
| RENESAS TECH CORP | 2 | 2004–2005 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 9 | 2000–2005 |
| Hyogo, JP | 8 | 2002–2016 |
| Toyama-shi, JP | 2 | 2021 |
| Himeji, JP | 2 | 2018–2021 |
| Ishikawa-gun, JP | 1 | 2021 |