Inventor

Junli Wang

Inventor

Slingerlands, NY, US

Overview

2000–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 310 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary

H01LSemiconductor devices31%

H10DInorganic electric semiconductor devices30%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%

H10BElectronic memory devices2%

B82YSpecific uses or applications of nanostructures1%

H05KPrinted circuits1%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%

C23CCoating metallic material0%

G11CStatic stores0%

PatentTitleYear

10,840,373Integration of input/output device in vertical field-effect transistor technology2020 10,840,147Fin cut forming single and double diffusion breaks2020 10,833,147Metal-insulator-metal capacitor structure2020 10,833,180Self-aligned tunneling field effect transistors2020 10,833,204Multiple width nanosheet devices2020 10,833,149Capacitors2020 10,833,155Vertical field effect transistor with top and bottom airgap spacers2020 10,832,975Reduced static random access memory (SRAM) device foot print through controlled bottom source/drain placement2020 10,825,890Metal-insulator-metal capacitor structure2020 10,825,891Metal-insulator-metal capacitor structure2020 10,811,528Two step fin etch and reveal for VTFETs and high breakdown LDVTFETs2020 10,811,507Vertical transistors having multiple gate thicknesses for optimizing performance and device density2020 10,811,508Vertical transistors having multiple gate thicknesses for optimizing performance and device density2020 10,804,368Semiconductor device having two-part spacer2020 10,797,163Leakage control for gate-all-around field-effect transistor devices2020 10,784,159Semiconductor device and method of forming the semiconductor device2020 10,777,469Self-aligned top spacers for vertical FETs with in situ solid state doping2020 10,755,985Gate metal patterning for tight pitch applications2020 10,741,544Integration of electrostatic discharge protection into vertical fin technology2020 10,734,372Vertical transport static random-access memory cells with transistors of active regions arranged in linear rows2020 10,734,504Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures2020 10,734,289Method for forming strained fin channel devices2020 10,714,596Directional deposition of protection layer2020 10,707,128Fabrication of self-aligned gate contacts and source/drain contacts directly above gate electrodes and source/drains2020 10,699,962FinFET devices2020 10,692,989Replacement metal gate structures2020 10,692,778Gate-all-around FETs having uniform threshold voltage2020 10,679,993Vertical fin field effect transistor devices with a replacement metal gate2020 10,672,887Vertical FET with shaped spacer to reduce parasitic capacitance2020 10,672,705Method of forming a straight via profile with precise critical dimension control2020 10,636,738Contacts having a geometry to reduce resistance2020 10,629,443Bottom source/drain silicidation for vertical field-effect transistor (FET)2020 10,628,404Vertical transistor and method of forming the vertical transistor2020 10,622,301Method of forming a straight via profile with precise critical dimension control2020 10,622,458Self-aligned contact for vertical field effect transistor2020 10,615,276Integration of input/output device in vertical field-effect transistor technology2020 10,615,082VFET metal gate patterning for vertical transport field effect transistor2020 10,600,694Gate metal patterning for tight pitch applications2020 10,593,679Static random access memory (SRAM) density scaling by using middle of line (MOL) flow2020 10,593,779Replacement metal gate structures2020 10,593,797Vertical transport field effect transistor structure with self-aligned top junction through early top source/drain epitaxy2020 10,593,803Self-aligned shallow trench isolation and doping for vertical fin transistors2020 10,586,857Replacement metal gate structures2020 10,586,867Strained FinFET source drain isloation2020 10,586,739Self-aligned punch through stopper liner for bulk FinFET2020 10,580,880Replacement metal gate structures2020 10,573,726Replacement metal gate structures2020 10,573,727Vertical transistor device2020 10,573,521Gate metal patterning to avoid gate stack attack due to excessive wet etching2020 10,566,453Vertical transistor contact for cross-coupling in a memory cell2020 10,566,246Shared contact trench comprising dual silicide layers and dual epitaxial layers for source/drain layers of NFET and PFET devices2020 10,559,572Vertical transistor contact for a memory cell with increased density2020 10,553,716Formation of a bottom source-drain for vertical field-effect transistors2020 10,541,312Air-gap top spacer and self-aligned metal gate for vertical fets2020 10,541,331Fabrication of a vertical fin field effect transistor with an asymmetric gate structure2020 10,529,858FinFET with merge-free fins2020 10,516,064Multiple width nanosheet devices2019 10,515,859Extra gate device for nanosheet2019 10,504,889Integrating a junction field effect transistor into a vertical field effect transistor2019 10,497,629Self-aligned punch through stopper liner for bulk FinFET2019 10,475,904Methods of forming merged source/drain regions on integrated circuit products2019 10,468,491Low resistance contact for transistors2019 10,460,990Semiconductor via structure with lower electrical resistance2019 10,453,934Vertical transport FET devices having air gap top spacer2019 10,446,670Integration of strained silicon germanium PFET device and silicon NFET device for FINFET structures2019 10,438,850Semiconductor device with local connection2019 10,431,495Semiconductor device with local connection2019 10,418,462Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process2019 10,418,280Fabrication of self-aligned gate contacts and source/drain contacts directly above gate electrodes and source/drains2019 10,411,128Strained fin channel devices2019 10,403,740Gate planarity for FinFET using dummy polish stop2019 10,396,069Approach to fabrication of an on-chip resistor with a field effect transistor2019 10,396,185Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures2019 10,388,718Metal-insulator-metal capacitor structure2019 10,388,576Semiconductor device including dual trench epitaxial dual-liner contacts2019 10,374,035Bulk nanosheet with dielectric isolation2019 10,373,905Integrating metal-insulator-metal capacitors with air gap process flow2019 10,361,265Precision BEOL resistors2019 10,347,759Vertical FET structure2019 10,340,189Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices2019 10,340,330Precision BEOL resistors2019 10,332,955Precision BEOL resistors2019 10,332,796Fin pitch scaling for high voltage devices and low voltage devices on the same wafer2019 10,332,956Precision beol resistors2019 10,326,017Formation of a bottom source-drain for vertical field-effect transistors2019 10,325,999Contact area to trench silicide resistance reduction by high-resistance interface removal2019 10,319,640FinFET devices2019 10,319,816Silicon germanium fin channel formation2019 10,319,852Forming eDRAM unit cell with VFET and via capacitance2019 10,312,346Vertical transistor with variable gate length2019 10,312,323Bulk nanosheet with dielectric isolation2019 10,312,349Reducing resistance of bottom source/drain in vertical channel devices2019 10,312,318Metal-insulator-metal capacitor structure2019 10,312,371Self-aligned shallow trench isolation and doping for vertical fin transistors2019 10,304,941Replacement metal gate structures2019 10,304,741Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices2019 10,297,689Precise control of vertical transistor gate length2019 10,297,448SiGe fins formed on a substrate2019 10,290,633CMOS compatible fuse or resistor using self-aligned contacts2019 10,283,636Vertical FET with strained channel2019 10,283,418Method of forming silicon germanium and silicon fins on oxide from bulk wafer2019 10,283,406Fabrication of self-aligned gate contacts and source/drain contacts directly above gate electrodes and source/drains2019 10,283,586Capacitors2019 10,276,658FinFET devices2019 10,276,558Electrostatic discharge protection using vertical fin CMOS technology2019 10,269,644Fin pitch scaling for high voltage devices and low voltage devices on the same wafer2019 10,256,145Semiconductor device and method of forming the semiconductor device2019 10,256,154Uniform shallow trench isolation2019 10,249,754Precise junction placement in vertical semiconductor devices using etch stop layers2019 10,249,753Gate cut on a vertical field effect transistor with a defined-width inorganic mask2019 10,249,537Method and structure for forming FinFET CMOS with dual doped STI regions2019 10,243,043Self-aligned air gap spacer for nanosheet CMOS devices2019 10,243,073Vertical channel field-effect transistor (FET) process compatible long channel transistors2019 10,236,293FinFET CMOS with silicon fin N-channel FET and silicon germanium fin P-channel FET2019 10,236,212Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices2019 10,236,289Approach to fabrication of an on-chip resistor with a field effect transistor2019 10,236,255Contact having self-aligned air gap spacers2019 10,236,380Precise control of vertical transistor gate length2019 10,236,359Replacement metal gate structures2019 10,236,219VFET metal gate patterning for vertical transport field effect transistor2019 10,224,429Precise junction placement in vertical semiconductor devices using etch stop layers2019 10,224,247FinFET devices2019 10,224,249Merged gate for vertical transistors2019 10,217,840Replacement metal gate structures2019 10,217,863Fabrication of a vertical fin field effect transistor with an asymmetric gate structure2019 10,211,316Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process2019 10,177,256Replacement metal gate structures2019 10,170,540Capacitors2019 10,170,425Microstructure of metal interconnect layer2019 10,164,060Work function metal fill for replacement gate fin field effect transistor process2018 10,157,797FinFET devices2018 10,157,912CMOS compatible fuse or resistor using self-aligned contacts2018 10,147,803Work function metal fill for replacement gate fin field effect transistor process2018 10,141,426Vertical transistor device2018 10,141,402FinFET devices2018 10,103,065Gate metal patterning for tight pitch applications2018 10,096,484Vertical transistor with a body contact for back-biasing2018 10,090,202Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices2018 10,090,411Air-gap top spacer and self-aligned metal gate for vertical fets2018 10,090,302Self-aligned shallow trench isolation and doping for vertical fin transistors2018 10,084,065Reducing resistance of bottom source/drain in vertical channel devices2018 10,083,862Protective liner between a gate dielectric and a gate contact2018 10,079,232FinFET CMOS with silicon fin n-channel FET and silicon germanium fin p-channel FET2018 10,074,577Silicon germanium and silicon fins on oxide from bulk wafer2018 10,068,970Nanowire isolation scheme to reduce parasitic capacitance2018 10,068,807Uniform shallow trench isolation2018 10,062,785Fin field-effect transistor (FinFET) with reduced parasitic capacitance2018 10,062,783Silicon germanium fin channel formation2018 10,056,366Gate stack integrated metal resistors2018 10,056,489Replacement metal gate structures2018 10,056,367Gate stack integrated metal resistors2018 10,050,141Precise control of vertical transistor gate length2018 10,050,121Replacement metal gate structures2018 10,043,747Vertical fuse structures2018 10,032,717Vertical fuse structures2018 10,032,711Integrating metal-insulator-metal capacitors with air gap process flow2018 10,032,769Cmos compatible fuse or resistor using self-aligned contacts2018 10,020,255Integration of super via structure in BEOL2018 10,020,254Integration of super via structure in BEOL2018 10,014,255Contacts having a geometry to reduce resistance2018 10,014,221FinFET devices2018 10,002,962Vertical FET structure2018 9,991,267Forming eDRAM unit cell with VFET and via capacitance2018 9,966,308Semiconductor device and method of forming the semiconductor device2018 9,966,454Contact area to trench silicide resistance reduction by high-resistance interface removal2018 9,954,107Strained FinFET source drain isolation2018 9,954,101Precise junction placement in vertical semiconductor devices using etch stop layers2018 9,954,058Self-aligned air gap spacer for nanosheet CMOS devices2018 9,947,593Extra gate device for nanosheet2018 9,947,663FinFET CMOS with silicon fin N-channel FET and silicon germanium fin P-channel FET2018 9,947,791FinFET with merge-free fins2018 9,941,392Gate planarity for FinFET using dummy polish stop2018 9,941,378Air-gap top spacer and self-aligned metal gate for vertical FETs2018 9,929,091'Vertical fuse structures'2018 9,917,081'Semiconductor device including finFET and fin varactor'2018 9,917,082'Approach to fabrication of an on-chip resistor with a field effect transistor'2018 9,917,105'Replacement fin process in SSOI wafer'2018 9,911,601'Epitaxial silicon germanium fin formation using sacrificial silicon fin templates'2018 9,911,657'Semiconductor device including finFET and fin varactor'2018 9,911,663'Preventing buried oxide gouging during planar and FinFET processing on SOI'2018 9,911,738'Vertical-transport field-effect transistors with a damascene gate strap'2018 9,905,469'Method and structure for forming FinFET CMOS with dual doped STI regions'2018 9,893,154'Recess liner for silicon germanium fin formation'2018 9,882,048'Gate cut on a vertical field effect transistor with a defined-width inorganic mask'2018 9,882,006'Silicon germanium fin channel formation'2018 9,881,869'Middle of the line integrated efuse in trench EPI structure'2018 9,881,926'Static random access memory (SRAM) density scaling by using middle of line (MOL) flow'2018 9,876,009CMOS compatible fuse or resistor using self-aligned contacts2018 9,871,116'Replacement metal gate structures'2018 9,865,739'Replacement metal gate structures'2018 9,853,022MIM capacitor formation in RMG module2017 9,853,127Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process2017 9,847,261Metal reflow for middle of line contacts2017 9,842,931'Self-aligned shallow trench isolation and doping for vertical fin transistors'2017 9,837,309Semiconductor via structure with lower electrical resistance2017 9,837,535Directional deposition of protection layer2017 9,818,650'Extra gate device for nanosheet'2017 9,812,567'Precise control of vertical transistor gate length'2017 9,805,935'Bottom source/drain silicidation for vertical field-effect transistor (FET)'2017 9,805,987'Self-aligned punch through stopper liner for bulk FinFET'2017 9,799,765'Formation of a bottom source-drain for vertical field-effect transistors'2017 9,793,402'Retaining strain in finFET devices'2017 9,793,175'FinFET devices having gate dielectric structures with different thicknesses on same semiconductor structure'2017 9,786,656'Integration of bipolar transistor into complimentary metal-oxide-semiconductor process'2017 9,786,563'Fin pitch scaling for high voltage devices and low voltage devices on the same wafer'2017 9,780,091'Fin pitch scaling for high voltage devices and low voltage devices on the same wafer'2017 9,768,079'Extra gate device for nanosheet'2017 9,768,118'Contact having self-aligned air gap spacers'2017 9,761,496'Field effect transistor contacts'2017 9,761,500'FinFET devices having gate dielectric structures with different thicknesses on same semiconductor structure'2017 9,761,699'Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures'2017 9,755,071'Merged gate for vertical transistors'2017 9,748,380'Vertical transistor including a bottom source/drain region, a gate structure, and an air gap formed between the bottom source/drain region and the gate structure'2017 9,741,792'Bulk nanosheet with dielectric isolation'2017 9,741,577'Metal reflow for middle of line contacts'2017 9,735,246'Air-gap top spacer and self-aligned metal gate for vertical fets'2017 9,728,642'Retaining strain in finFET devices'2017 9,716,042'Fin field-effect transistor (FinFET) with reduced parasitic capacitance'2017 9,716,045'Directly forming SiGe fins on oxide'2017 9,704,990'Vertical FET with strained channel'2017 9,698,215'MIM capacitor formation in RMG module'2017 9,698,098'Anti-fuse structure and method for manufacturing the same'2017 9,698,226'Recess liner for silicon germanium fin formation'2017 9,698,212'Three-dimensional metal resistor formation'2017 9,691,877'Replacement metal gate structures'2017 9,685,532'Replacement metal gate structures'2017 9,685,507'FinFET devices'2017 9,685,539'Nanowire isolation scheme to reduce parasitic capacitance'2017 9,673,199'Gate cutting for a vertical transistor device'2017 9,666,533'Airgap formation between source/drain contacts and gates'2017 9,666,527'Middle of the line integrated eFuse in trench EPI structure'2017 9,653,575'Vertical transistor with a body contact for back-biasing'2017 9,653,456'MIM capacitor formation in RMG module'2017 9,640,641'Silicon germanium fin channel formation'2017 9,634,005'Gate planarity for FinFET using dummy polish stop'2017 9,634,027'CMOS structure on SSOI wafer'2017 9,634,090'Preventing buried oxide gouging during planar and FinFET processing on SOI'2017 9,634,010'Field effect transistor device spacers'2017 9,627,373'CMOS compatible fuse or resistor using self-aligned contacts'2017 9,627,263'Stop layer through ion implantation for etch stop'2017 9,613,869'FinFET devices'2017 9,614,057'Enriched, high mobility strained fin having bottom dielectric isolation'2017 9,607,943'Capacitors'2017 9,607,903'Method for forming field effect transistors'2017 9,601,386'Fin isolation on a bulk wafer'2017 9,576,980'FinFET devices having gate dielectric structures with different thicknesses on same semiconductor structure'2017 9,570,571'Gate stack integrated metal resistors'2017 9,570,591'Forming semiconductor device with close ground rules'2017 9,570,555'Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices'2017 9,564,437'Method and structure for forming FinFET CMOS with dual doped STI regions'2017 9,559,014'Self-aligned punch through stopper liner for bulk FinFET'2017 9,553,088'Forming semiconductor device with close ground rules'2017 9,548,388'Forming field effect transistor device spacers'2017 9,536,986'Enriched, high mobility strained fin having bottom dielectric isolation'2017 9,536,988'Parasitic capacitance reduction'2017 9,530,698'Method and structure for forming FinFET CMOS with dual doped STI regions'2016 9,530,651'Replacement metal gate finFET'2016 9,530,659'Structure for preventing buried oxide gouging during planar and FinFET Processing on SOI'2016 9,530,890'Parasitic capacitance reduction'2016 9,520,392'Semiconductor device including finFET and fin varactor'2016 9,520,357'Anti-fuse structure and method for manufacturing the same'2016 9,515,070'Replacement metal gate'2016 9,508,741'CMOS structure on SSOI wafer'2016 9,508,825'Method and structure for forming gate contact above active area with trench silicide'2016 9,508,818'Method and structure for forming gate contact above active area with trench silicide'2016 9,496,281'Dual isolation on SSOI wafer'2016 9,490,252'MIM capacitor formation in RMG module'2016 9,490,253'Gate planarity for finFET using dummy polish stop'2016 9,490,335'Extra gate device for nanosheet'2016 9,484,201'Epitaxial silicon germanium fin formation using sacrificial silicon fin templates'2016 9,484,264'Field effect transistor contacts'2016 9,472,407'Replacement metal gate FinFET'2016 9,472,670'Field effect transistor device spacers'2016 9,455,274'Replacement fin process in SSOI wafer'2016 9,443,977'FinFET with reduced source and drain resistance'2016 9,437,436'Replacement metal gate FinFET'2016 9,431,425'Directly forming SiGe fins on oxide'2016 9,418,900'Silicon germanium and silicon fins on oxide from bulk wafer'2016 9,406,746'Work function metal fill for replacement gate fin field effect transistor process'2016 9,401,372'Dual isolation on SSOI wafer'2016 9,397,215'FinFET with reduced source and drain resistance'2016 9,379,221'Bottom-up metal gate formation on replacement metal gate finFET devices'2016 9,373,618'Integrated FinFET capacitor'2016 9,337,254'Integrated FinFET capacitor'2016 9,293,464'Structure to enhance gate induced strain effect in multigate devices'2016 9,276,013'Integrated formation of Si and SiGe fins'2016 9,231,080'Replacement metal gate'2016 9,153,447'Replacement metal gate FinFET'2015 9,105,662'Method and structure to enhance gate induced strain effect in multigate device'2015 9,099,493'Semiconductor device with raised source/drain and replacement metal gate'2015 9,093,376'Replacement metal gate FinFET'2015 9,059,019'Semiconductor device including source/drain formed on bulk and gate channel formed on oxide layer'2015 9,059,217'FET semiconductor device with low resistance and enhanced metal fill'2015 9,029,208'Semiconductor device with replacement metal gate and method for selective deposition of material for replacement metal gate'2015 8,999,815'Method to form finFET/trigate devices on bulk semiconductor wafers'2015 8,957,478'Semiconductor device including source/drain formed on bulk and gate channel formed on oxide layer'2015 8,866,204'Method to form finFET/trigate devices on bulk semiconductor wafers'2014 8,857,209'Apparatus for carrying/storing baked goods and the like'2014 8,815,734'Use of gas cluster ion beam to reduce metal void formation in interconnect structures'2014 8,786,030'Gate-last fabrication of quarter-gap MGHK FET'2014

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2009–2013Patents assigned to SONY CORP (4)· patent assignee history

2009–2013Based in Kanagawa, JP· patent location history

2013–2020Patents assigned to IBM (297)· patent assignee history

2013–2020Patents assigned to GLOBALFOUNDRIES INC (20)· patent assignee history

2013–2014Patents assigned to WANG JUNLI (7)· patent assignee history

2013–2020Based in Slingerlands, NY, US· patent location history

2013–2020Based in Singerlands, NY, US· patent location history

2014–2020Patents assigned to ST MICROELECTRONICS INC (13)· patent assignee history

2018–2020Based in Albany, NY, US· patent location history

2019Based in Slingerland, NY, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	297	2013–2020
GLOBALFOUNDRIES INC	20	2013–2020
ST MICROELECTRONICS INC	13	2014–2020
WANG JUNLIself	7	2013–2014
SONY CORP	4	2009–2013

Locations

Location	Patents	Span
Slingerlands, New York, US	199	2013–2020
Singerlands, New York, US	86	2013–2020
Albany, New York, US	17	2018–2020
Kanagawa, JP	4	2009–2013
Slingerland, New York, US	1	2019