Inventor

Donald W. Plass

Inventor

Poughkeepsie, NY, US

Overview

1990–2021

Patent span

Physics

Primary field (CPC G)

Patents· 56 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores68%

G06FElectric digital data processing10%

G01RMeasuring electric variables4%

H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems4%

H03KPulse technique4%

H10BElectronic memory devices4%

G05FSystems for regulating electric or magnetic variables3%

H01LSemiconductor devices1%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%

PatentTitleYear

10,943,647Bit-line mux driver with diode header for computer memory2021 10,930,339Voltage bitline high (VBLH) regulation for computer memory2021 10,832,756Negative voltage generation for computer memory2020 10,762,953Memory array with reduced circuitry2020 10,559,346Bias-controlled bit-line sensing scheme for eDRAM2020 9,748,958'Dynamic high voltage driver with adjustable clamped output level'2017 9,341,655'Charge pump generator with direct voltage sensor'2016 9,299,458'Voltage comparator circuit and usage thereof'2016 9,263,096'Voltage comparator circuit and usage thereof'2016 9,250,271'Charge pump generator with direct voltage sensor'2016 9,224,437'Gated-feedback sense amplifier for single-ended local bit-line memories'2015 9,099,200'SRAM restore tracking circuit and method'2015 9,053,770'Dynamic cascode-managed high-voltage word-line driver circuit'2015 9,047,930'Single-ended low-swing power-savings mechanism with process compensation'2015 9,025,403'Dynamic cascode-managed high-voltage word-line driver circuit'2015 8,937,840'Digital voltage boost circuit'2015 8,605,528'Sense amplifier having an isolated pre-charge architecture, a memory circuit incorporating such a sense amplifier and associated methods'2013 8,472,271'Systems and methods for memory device precharging'2013 8,258,758'System to improve a multistage charge pump and associated methods'2012 8,214,592'Dynamic runtime modification of array layout for offset'2012 8,120,968'High voltage word line driver'2012 7,953,987'Protection of secure electronic modules against attacks'2011 7,793,173'Efficient memory product for test and soft repair of SRAM with redundancy'2010 7,787,284'Integrated circuit chip with improved array stability'2010 7,688,650'Write control method for a memory array configured with multiple memory subarrays'2010 7,606,060'Eight transistor SRAM cell with improved stability requiring only one word line'2009 7,471,590'Write control circuitry and method for a memory array configured with multiple memory subarrays'2008 7,437,626'Efficient method of test and soft repair of SRAM with redundancy'2008 7,403,412'Integrated circuit chip with improved array stability'2008 7,380,191'ABIST data compression and serialization for memory built-in self test of SRAM with redundancy'2008 7,299,374'Clock control method and apparatus for a memory array'2007 7,295,458'Eight transistor SRAM cell with improved stability requiring only one word line'2007 7,295,457'Integrated circuit chip with improved array stability'2007 7,283,417'Write control circuitry and method for a memory array configured with multiple memory subarrays'2007 7,266,737'Method for enabling scan of defective ram prior to repair'2007 7,233,542'Method and apparatus for address generation'2007 7,219,275'Method and apparatus for providing flexible modular redundancy allocation for memory built in self test of SRAM with redundancy'2007 7,210,084'Integrated system logic and ABIST data compression for an SRAM directory'2007 7,176,725'Fast pulse powered NOR decode apparatus for semiconductor devices'2007 7,173,875'SRAM array with improved cell stability'2007 7,170,320'Fast pulse powered NOR decode apparatus with pulse stretching and redundancy steering'2007 7,102,944'Programmable analog control of a bitline evaluation circuit'2006 7,099,206'High density bitline selection apparatus for semiconductor memory devices'2006 7,099,203'Circuit and method for writing a binary value to a memory cell'2006 7,088,638'Global and local read control synchronization method and system for a memory array configured with multiple memory subarrays'2006 7,085,173'Write driver circuit for memory array'2006 7,075,855'Memory output timing control circuit with merged functions'2006 7,068,554'Apparatus and method for implementing multiple memory redundancy with delay tracking clock'2006 7,064,990'Method and apparatus for implementing multiple column redundancy for memory'2006 7,023,759'System and method for synchronizing memory array signals'2006 7,009,895'Method for skip over redundancy decode with very low overhead'2006 6,822,885'High speed latch and compare function'2004 6,737,685'Compact SRAM cell layout for implementing one-port or two-port operation'2004 6,728,912'SOI cell stability test method'2004 6,584,023'System for implementing a column redundancy scheme for arrays with controls that span multiple data bits'2003 4,901,279'MESFET sram with power saving current-limiting transistors'1990

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1990–2021Patents assigned to IBM (54)· patent assignee history

1990–2007Based in Pleasant Valley, NY, US· patent location history

2006–2021Based in Poughkeepsie, NY, US· patent location history

2007–2010Based in Putman Valley, NY, US· patent location history

2012–2015Patents assigned to PLASS DONALD W (6)· patent assignee history

2013–2015Patents assigned to DAWSON JAMES W (2)· patent assignee history

2013–2015Patents assigned to JUNGMANN NOAM (2)· patent assignee history

2015–2016Patents assigned to GLOBALFOUNDRIES INC (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	54	1990–2021
PLASS DONALD Wself	6	2012–2015
GLOBALFOUNDRIES INC	3	2015–2016
DAWSON JAMES W	2	2013–2015
JUNGMANN NOAM	2	2013–2015

Locations

Location	Patents	Span
Poughkeepsie, New York, US	45	2006–2021
Pleasant Valley, New York, US	7	1990–2007
Putman Valley, New York, US	4	2007–2010