Inventor
Vedvyas Shanbhogue
Inventor
Austin, TX, US
Overview
Patents· 117 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing72%
H04LTransmission of digital information, e.g. telegraphic communication13%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use10%
G01RMeasuring electric variables2%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%
G11CStatic stores1%
PatentTitleYear
11,099,878Scalable virtual machine operation inside trust domains within the trust domain architecture202111,099,880Virtualization of process address space identifiers for scalable virtualization of input/output devices202111,099,847Mode-specific endbranch for control flow termination202111,082,231Indirection directories for cryptographic memory protection202111,070,527Securing platform link with encryption202111,055,236Processors, methods, systems, and instructions to support live migration of protected containers202111,055,094Heterogeneous CPUID spoofing for remote processors202111,029,957Apparatuses, methods, and systems for instructions to compartmentalize code202111,029,952Hardware apparatuses and methods to switch shadow stack pointers202111,023,232Control transfer termination instructions of an instruction set architecture (ISA)202110,962,596System, apparatus and method for in-field self testing in a diagnostic sleep state202110,949,207Processor core supporting a heterogeneous system instruction set architecture202110,922,241Supporting secure memory intent202110,901,940Processors, methods, systems, and instructions to atomically store to memory data wider than a natively supported data width202110,901,772Virtualization exceptions202110,877,751Spoofing a processor identification instruction202010,860,709Encoded inline capabilities202010,831,679Systems, methods, and apparatuses for defending against cross-privilege linear probes202010,795,829Device, method and system to selectively provide data validation functionality202010,761,996Apparatus and method for secure memory access using trust domains202010,713,177Defining virtualized page attributes based on guest page attributes202010,705,976Scalable processor-assisted guest physical address translation202010,706,164Crypto-enforced capabilities for isolation202010,678,575Instruction-set support for invocation of VMM-configured services without VMM intervention202010,671,547Lightweight trusted tasks202010,671,542Application execution enclave memory method and apparatus202010,628,315Secure memory repartitioning technologies202010,620,266System, apparatus and method for in-field self testing in a diagnostic sleep state202010,620,969System, apparatus and method for providing hardware feedback information in a processor202010,592,421Instructions and logic to provide advanced paging capabilities for secure enclave page caches202010,558,588Processors, methods, systems, and instructions to support live migration of protected containers202010,545,883Verification bit for one-way encrypted memory202010,536,264Efficient cryptographically secure control flow integrity protection202010,534,724Instructions and logic to suspend/resume migration of enclaves in a secure enclave page cache202010,515,023System for address mapping and translation protection201910,503,664Virtual machine manager for address mapping and translation protection201910,496,573Context-sensitive interrupts201910,445,494Attack protection for valid gadget control transfers201910,437,623Fast switching between virtual machines without interrupt virtualization for high-performance, secure trusted-execution environment201910,430,580Processor extensions to protect stacks during ring transitions201910,409,597Memory management in secure enclaves201910,402,218Detecting bus locking conditions and avoiding bus locks201910,394,556Hardware apparatuses and methods to switch shadow stack pointers201910,394,595Method to manage guest address space trusted by virtual machine monitor201910,366,228Detection and mitigation of malicious invocation of sensitive code201910,360,374Techniques for control flow protection201910,324,862Supporting oversubscription of guest enclave memory pages201910,296,366Virtualization exceptions201910,289,554Supporting fault information delivery201910,282,306Supporting secure memory intent201910,262,162Control transfer termination instructions of an instruction set architecture (ISA)201910,255,196Method and apparatus for sub-page write protection201910,216,648Maintaining a secure processing environment across power cycles201910,120,805Managing memory for secure enclaves201810,075,296Loading and virtualizing cryptographic keys20189,990,314Instructions and logic to interrupt and resume paging in a secure enclave page cache20189,990,197Memory management in secure enclaves20189,965,619Return address overflow buffer20189,886,577'Detection and mitigation of malicious invocation of sensitive code'20189,875,189Supporting secure memory intent20189,858,411'Execution profiling mechanism'20189,804,870'Instruction-set support for invocation of VMM-configured services without VMM intervention'20179,804,871'Instruction-set support for invocation of VMM-configured services without VMM intervention'20179,798,666'Supporting fault information delivery'20179,792,222'Validating virtual address translation by virtual machine monitor utilizing address validation structure to validate tentative guest physical address and aborting based on flag in extended page table requiring an expected guest physical address in the address validation structure'20179,785,800'Non-tracked control transfers within control transfer enforcement'20179,766,889'Memory management in secure enclaves'20179,767,044'Secure memory repartitioning'20179,767,272'Attack Protection for valid gadget control transfers'20179,747,102'Memory management in secure enclaves'20179,710,401'Processors, methods, systems, and instructions to support live migration of protected containers'20179,703,703'Control of entry into protected memory views'20179,703,567'Control transfer termination instructions of an instruction set architecture (ISA)'20179,703,733'Instructions and logic to interrupt and resume paging in a secure enclave page cache'20179,690,704'Paging in secure enclaves'20179,684,608'Maintaining a secure processing environment across power cycles'20179,684,605'Translation lookaside buffer for guest physical addresses in a virtual machine'20179,684,511'Using software having control transfer termination instructions with software not having control transfer termination instructions'20179,665,373'Protecting confidential data with transactional processing in execute-only memory'20179,665,724'Logging in secure enclaves'20179,652,388'Method, apparatus and system for performing management component transport protocol (MCTP) communications with a universal serial bus (USB) device'20179,626,508'Providing supervisor control of control transfer execution profiling'20179,619,412'Enabling virtualization of a processor resource'20179,612,930'Providing autonomous self-testing of a processor'20179,563,455'Virtualization exceptions'20179,519,773'Returning to a control transfer instruction'20169,442,865'Processor extensions for execution of secure embedded containers'20169,430,384'Instructions and logic to provide advanced paging capabilities for secure enclave page caches'20169,355,262'Modifying memory permissions in a secure processing environment'20169,335,943'Method and apparatus for fine grain memory protection'20169,330,020'System, apparatus, and method for transparent page level instruction translation'20169,323,686'Paging in secure enclaves'20169,323,942'Protecting information processing system secrets from debug attacks'20169,323,564'Systems, methods and computer program products for bootstrapping a type 1 virtual machine monitor after operating system launch'20169,276,750'Secure processing environment measurement and attestation'20169,268,594'Processor extensions for execution of secure embedded containers'20169,245,106'Providing a multi-phase lockstep integrity reporting mechanism'20169,195,824'Providing integrity verification and attestation in a hidden execution environment'20159,189,411'Logging in secure enclaves'20159,189,620'Protecting a software component using a transition point wrapper'20159,141,570'Enabling virtualization of a processor resource'20159,086,913'Processor extensions for execution of secure embedded containers'20158,955,144'Protecting information processing system secrets from debug attacks'20158,887,267'Providing integrity verification and attestation in a hidden execution environment'20148,844,021'Providing a multi-phase lockstep integrity reporting mechanism'20148,806,104'Enabling virtualization of a processor resource'20148,694,636'Method and apparatus for network filtering and firewall protection on a secure partition'20148,646,052'Method and apparatus for providing a secure display window inside the primary display'20148,615,757'Negotiated assignment of resources to a virtual machine in a multi-virtual machine environment'20138,555,380'Automatic modification of executable code'20138,516,551'Providing a multi-phase lockstep integrity reporting mechanism'20138,510,569'Providing integrity verification and attestation in a hidden execution environment'20138,468,356'Software copy protection via protected execution of applications'20138,244,945'Efficient handling of interrupts in a computing environment'20128,190,778'Method and apparatus for network filtering and firewall protection on a secure partition'20127,414,976'Method and apparatus to implement operation and maintenance (OAM) functions on a network processor'20087,178,056'Rolling software upgrades for fault tolerant systems'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2021Patents assigned to INTEL CORP (114)· patent assignee history
2007Based in Los Angeles, CA, US· patent location history
2008Based in Beaverton, OR, US· patent location history
2012–2020Patents assigned to SHANBHOGUE VEDVYAS (20)· patent assignee history
2012–2018Patents assigned to SAHITA RAVI (3)· patent assignee history
2012–2016Patents assigned to SAVAGAONKAR UDAY (3)· patent assignee history
2012–2015Based in Portland, OR, US· patent location history
2014–2021Based in Austin, TX, US· patent location history
2015–2016Based in Bee Cave, TX, US· patent location history
2016–2019Patents assigned to HUNTLEY BARRY E (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 114 | 2007–2021 |
| SHANBHOGUE VEDVYASself | 20 | 2012–2020 |
| HUNTLEY BARRY E | 3 | 2016–2019 |
| SAHITA RAVI | 3 | 2012–2018 |
| SAVAGAONKAR UDAY | 3 | 2012–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 101 | 2014–2021 |
| Portland, OR, US | 11 | 2012–2015 |
| Bee Cave, Texas, US | 3 | 2015–2016 |
| Beaverton, OR, US | 1 | 2008 |
| Los Angeles, California, US | 1 | 2007 |