Inventor
Ji Pan
Inventor
San Jose, CA, US
Overview
Patents· 42 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices37%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1027%
H01LSemiconductor devices23%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems5%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
H03KPulse technique2%
H10BElectronic memory devices2%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation1%
PatentTitleYear
10,763,351Vertical trench DMOSFET having integrated implants forming enhancement diodes in parallel with the body diode202010,535,764Device and fabrication of MOS device with island region202010,388,781Device structure having inter-digitated back to back MOSFETs201910,325,908Compact source ballast trench MOSFET and method of manufacturing201910,256,236Forming switch circuit with controllable phase node ringing201910,192,982Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact201910,103,140Switch circuit with controllable phase node ringing201810,074,742MOS device with island region201810,062,685Variable snubber for MOSFET application20189,754,788'Manufacturing method of semiconductor structure including planarizing a polysilicon layer over an array area and a periphery area'20179,748,375'Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact'20179,685,435'Integrated snubber in a single poly MOSFET'20179,564,516'Method of making integrated MOSFET-schottky diode device with reduced source and body kelvin contact impedance and breakdown voltage'20179,356,022'Semiconductor device with termination structure for power MOSFET applications'20169,312,336'MOSFET device with reduced breakdown voltage'20169,281,394'Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact'20169,236,450'Fabrication of MOS device with schottky barrier controlling layer'20169,230,957'Integrated snubber in a single poly MOSFET'20169,117,695'Method for fabricating semiconductor device'20159,105,494'Termination trench for power MOSFET applications'20159,059,147'Junction barrier schottky (JBS) with floating islands'20159,006,053'Method of making MOSFET integrated with schottky diode with simplified one-time top-contact trench etching'20158,969,950'Integrated MOSFET-Schottky diode device with reduced source and body Kelvin contact impedance and breakdown voltage'20158,928,079'MOS device with low injection diode'20158,901,003'Polishing method of semiconductor structure'20148,809,143'Fabrication of MOS device with schottky barrier controlling layer'20148,785,278'Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact'20148,748,268'Method of making MOSFET integrated with schottky diode with simplified one-time top-contact trench etching'20148,728,890'Fabrication of MOS device with integrated Schottky diode in active region contact trench'20148,692,322'Flexible Crss adjustment in a SGT MOSFET to smooth waveforms and to avoid EMI in DC-DC application'20148,680,643'Junction barrier Schottky (JBS) with floating islands'20148,643,071'Integrated snubber in a single poly MOSFET'20148,586,435'Fabrication of MOSFET device with reduced breakdown voltage'20138,450,794'MOS device with varying contact trench lengths'20138,362,547'MOS device with Schottky barrier controlling layer'20138,362,552'MOSFET device with reduced breakdown voltage'20138,362,585'Junction barrier Schottky diode with enforced upper contact structure and method for robust packaging'20138,283,723'MOS device with low injection diode'20128,227,330'Junction barrier Schottky (JBS) with floating islands'20128,093,651'MOS device with integrated schottky diode in active region contact trench'20128,053,808'Layouts for multiple-stage ESD protection circuits for integrating with semiconductor power device'20117,671,439'Junction barrier Schottky (JBS) with floating islands'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2020Patents assigned to ALPHA & OMEGA SEMICONDUCTOR (38)· patent assignee history
2010–2015Based in Santa Clara, CA, US· patent location history
2012–2015Patents assigned to PAN JI (15)· patent assignee history
2012–2015Patents assigned to BHALLA ANUP (14)· patent assignee history
2012–2015Patents assigned to WANG XIAOBIN (6)· patent assignee history
2012–2020Based in San Jose, CA, US· patent location history
2013–2014Patents assigned to NG DANIEL (5)· patent assignee history
2014–2017Based in Beijing, CN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ALPHA & OMEGA SEMICONDUCTOR | 38 | 2010–2020 |
| PAN JIself | 15 | 2012–2015 |
| BHALLA ANUP | 14 | 2012–2015 |
| WANG XIAOBIN | 6 | 2012–2015 |
| NG DANIEL | 5 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 34 | 2012–2020 |
| Santa Clara, California, US | 5 | 2010–2015 |
| Beijing, CN | 3 | 2014–2017 |