LexDanaLexDanabeta
Inventor

Yueh-Se Ho

Inventor
Sunnyvale, CA, US

Overview

107→
Patents
1988–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 107 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1044%
H01LSemiconductor devices20%
H10DInorganic electric semiconductor devices15%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
H02JElectric power networks1%
H01JElectric discharge tubes or discharge lamps0%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems0%
Y10TTechnical subjects covered by former us classification0%
PatentTitleYear
10,991,680Common source land grid array package202110,991,660Semiconductor package having high mechanical strength202110,573,762Vertical gallium nitride Schottky diode202010,522,666Methods for fabricating anode shorted field stop insulated gate bipolar transistor201910,333,006Termination structure for gallium nitride Schottky diode including junction barriar diodes201910,050,134Methods for fabricating anode shorted field stop insulated gate bipolar transistor201810,038,106Termination structure for gallium nitride Schottky diode20189,929,076'Semiconductor package of a flipped MOSFET chip and a multi-based die paddle with top surface groove-divided multiple connecting areas for connection to the flipped MOSFET electrodes'20189,837,386Power device and preparation method thereof20179,786,583'Power semiconductor package device having locking mechanism, and preparation method thereof'20179,768,146'Battery protection package and process of making the same'20179,735,094'Combined packaged power semiconductor device'20179,728,655'Termination structure for gallium nitride schottky diode'20179,685,430'Embedded package and method thereof'20179,679,833'Semiconductor package with small gate clip and assembly method'20179,564,406'Battery protection package and process of making the same'20179,520,380'Wafer process for molded chip scale package (MCSP) with thick backside metallization'20169,478,646'Methods for fabricating anode shorted field stop insulated gate bipolar transistor'20169,472,491'Semiconductor package with small gate clip and assembly method'20169,437,530'Combined packaged power semiconductor device'20169,412,684'Top exposed semiconductor chip package'20169,406,661'Protection circuit including vertical gallium nitride schottky diode and PN junction diode'20169,397,029'Power semiconductor package device having locking mechanism, and preparation method thereof'20169,391,005'Method for packaging a power device with bottom source electrode'20169,337,132'Methods and configuration for manufacturing flip chip contact (FCC) power package'20169,305,870'Power semiconductor device and preparation method thereof'20169,281,265'Packaging structure of a semiconductor device'20169,269,699'Embedded package and method thereof'20169,245,861'Wafer process for molded chip scale package (MCSP) with thick backside metallization'20169,214,419'Power semiconductor device and preparation method thereof'20159,214,417'Combined packaged power semiconductor device'20159,196,534'Method for preparing semiconductor devices applied in flip chip technology'20159,184,117'Stacked dual-chip packaging structure and preparation method thereof'20159,171,788'Semiconductor package with small gate clip and assembly method'20159,165,866'Stacked dual chip package having leveling projections'20159,136,379'Bottom source substrateless power MOSFET'20159,136,154'Substrateless power device packages'20159,040,356'Semiconductor including cup-shaped leadframe packaging techniques'20158,994,140'Vertical gallium nitride Schottky diode'20158,987,878'Substrateless power device packages'20158,981,464'Wafer level chip scale package and process of manufacture'20158,952,509'Stacked multi-chip bottom source semiconductor device and preparation method thereof'20158,933,518'Stacked power semiconductor device using dual lead frame'20158,890,296'Wafer level chip scale package'20148,865,523'Semiconductor package and fabrication method thereof'20148,815,649'Multi-layer lead frame package and method of fabrication'20148,796,858'Virtually substrate-less composite power semiconductor device'20148,785,296'Packaging method with backside wafer dicing'20148,778,735'Packaging method of molded wafer level chip scale package (WLCSP)'20148,772,144'Vertical gallium nitride Schottky diode'20148,716,063'Wafer level chip scale package and process of manufacture'20148,716,069'Semiconductor device employing aluminum alloy lead-frame with anodized aluminum'20148,686,546'Combined packaged power semiconductor device'20148,642,385'Wafer level package structure and the fabrication method thereof'20148,586,414'Top exposed package and assembly method'20138,581,376'Stacked dual chip package and method of fabrication'20138,569,169'Bottom source power MOSFET with substrateless and manufacturing method thereof'20138,564,049'Flip chip contact (FCC) power package'20138,564,110'Power device with bottom source electrode'20138,563,417'Method for packaging ultra-thin chip with solder ball thermo-compression in wafer level packaging process'20138,563,361'Packaging method of molded wafer level chip scale package (WLCSP)'20138,513,784'Multi-layer lead frame package and method of fabrication'20138,481,368'Semiconductor package of a flipped MOSFET and its manufacturing method'20138,476,752'Package structure for DC-DC converter'20138,436,429'Stacked power semiconductor device using dual lead frame and manufacturing method'20138,426,960'Wafer level chip scale packaging'20138,362,606'Wafer level chip scale package'20138,330,264'Packaging configurations for vertical electronic devices using conductive traces disposed on laminated board layers'20128,242,013'Virtually substrate-less composite power semiconductor device and method'20128,217,503'Package structure for DC-DC converter'20128,169,062'Integrated circuit package for semiconductior devices with improved electric resistance and inductance'20128,168,477'Packaging configurations for vertical electronic devices using conductive traces disposed on laminated board layers'20128,124,453'Vertically packaged MOSFET and IC power devices as integrated module using 3D interconnected laminates'20128,067,822'Integrated circuit package for semiconductor devices with improved electric resistance and inductance'20118,058,727'Standing chip scale package'20118,053,891'Standing chip scale package'20117,955,893'Wafer level chip scale package and process of manufacture'20117,838,977'Packages for electronic devices implemented with laminated board with a top and a bottom patterned metal layers'20107,829,989'Vertical packaged IC device modules with interconnected 3D laminates directly contacts wafer backside'20107,811,904'Method of fabricating a semiconductor device employing electroless plating'20107,633,140'Inverted J-lead for power devices'20097,595,547'Semiconductor die package including cup-shaped leadframe'20097,589,396'Chip scale surface mount package for semiconductor device and process of fabricating the same'20097,391,100'Integrated circuit package for semiconductor devices having a reduced leadframe pad and an increased bonding area'20087,211,877'Chip scale surface mount package for semiconductor device and process of fabricating the same'20077,208,818'Power semiconductor package'20077,183,616'High speed switching MOSFETS using multi-parallel die packages with/without special leadframes'20076,909,170'Semiconductor assembly with package using cup-shaped lead-frame'20056,876,061'Chip scale surface mount package for semiconductor device and process of fabricating the same'20056,841,852'Integrated circuit package for semiconductor devices with improved electric resistance and inductance'20056,744,124'Semiconductor die package including cup-shaped leadframe'20046,562,647'Chip scale surface mount package for semiconductor device and process of fabricating the same'20036,441,475'Chip scale surface mount package for semiconductor device and process of fabricating the same'20026,392,290'Vertical structure for semiconductor wafer-level chip scale packages'20026,316,287'Chip scale surface mount packages for semiconductor device and process of fabricating the same'20016,271,060'Process of fabricating a chip scale surface mount package for semiconductor device'20016,249,041'IC chip package with directly connected leads'20015,904,525'Fabrication of high-density trench DMOS using sidewall spacers'19995,767,578'Surface mount and flip chip technology with diamond film passivation for total integated circuit isolation'19985,757,081'Surface mount and flip chip technology for total integrated circuit isolation'19985,753,529'Surface mount and flip chip technology for total integrated circuit isolation'19985,750,416'Method of forming a lateral field effect transistor having reduced drain-to-source on-resistance'19985,639,676'Trenched DMOS transistor fabrication having thick termination region oxide'19975,578,851'Trenched DMOS transistor having thick field oxide in termination region'19965,468,982'Trenched DMOS transistor with channel block at cell trench corners'19955,316,959'Trenched DMOS transistor fabrication using six masks'19944,738,761'Shared current loop, multiple field apparatus and process for plasma processing'1988

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1988Based in Raleigh, NC, US· patent location history
1994–2021Based in Sunnyvale, CA, US· patent location history
2007–2020Patents assigned to ALPHA & OMEGA SEMICONDUCTOR (81)· patent assignee history
2011–2016Patents assigned to HO YUEH-SE (37)· patent assignee history
2012–2018Patents assigned to XUE YAN XUN (26)· patent assignee history
2012–2018Patents assigned to LU JUN (21)· patent assignee history
2013–2018Patents assigned to YILMAZ HAMZA (14)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ALPHA & OMEGA SEMICONDUCTOR812007–2020
HO YUEH-SEself372011–2016
XUE YAN XUN262012–2018
LU JUN212012–2018
YILMAZ HAMZA142013–2018
Locations
LocationPatentsSpan
Sunnyvale, California, US1061994–2021
Raleigh, NC, US11988