Inventor
Laura S. Chadwick
Inventor
Essex Junction, VT, US
Overview
Patents· 9 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing60%
G11CStatic stores20%
G01RMeasuring electric variables10%
H10DInorganic electric semiconductor devices10%
PatentTitleYear
9,754,071'Integrated circuit (IC) design analysis and feature extraction'20177,890,906'Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells'20117,877,714'System and method to optimize semiconductor power by integration of physical design timing and product performance measurements'20117,849,433'Integrated circuit with uniform polysilicon perimeter density, method and design structure'20107,810,054'Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut point'20107,805,693'IC chip design modeling using perimeter density to electrical characteristic correlation'20107,487,487'Design structure for monitoring cross chip delay variation on a semiconductor device'20097,237,165'Method for testing embedded DRAM arrays'20077,073,100'Method for testing embedded DRAM arrays'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2011Patents assigned to IBM (8)· patent assignee history
2006–2017Based in Essex Junction, VT, US· patent location history
2017Patents assigned to GLOBALFOUNDRIES INC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 8 | 2006–2011 |
| GLOBALFOUNDRIES INC | 1 | 2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Essex Junction, VT, US | 9 | 2006–2017 |