Inventor
James W. Alexander
Inventor
Hillsboro, OR, US
Overview
Patents· 39 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing33%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use16%
G11CStatic stores9%
H04LTransmission of digital information, e.g. telegraphic communication9%
G05BControl or regulating systems in general5%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes5%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications5%
Y04SSystems integrating technologies related to power network operation, communication or information technologies for improving the electrical power generation, transmission, distribution, management or usage, i.e. smart grids5%
B60PVehicles adapted for load transportation or to transport, to carry, or to comprise special loads or objects2%
B60RVehicles, vehicle fittings, or vehicle parts, not otherwise provided for2%
PatentTitleYear
10,712,796Method and apparatus to generate and use power, thermal and performance characteristics of nodes to improve energy efficiency and reducing wait time for jobs in the queue202010,289,183Methods and apparatus to manage jobs that can and cannot be suspended when there is a change in power allocation to a distributed computer system201910,073,659Power management circuit with per activity weighting and multiple throttle down thresholds201810,037,069Dynamic link width modulation20189,927,857'Profiling a job power and energy consumption for a data processing system'20189,921,633'Power aware job scheduler and manager for a data processing system'20189,588,823'Adjustment of execution of tasks'20179,575,536'Methods and apparatus to estimate power performance of a job that runs on multiple nodes of a distributed computer system'20179,568,978'Controlling power consumption in processor-based systems and components thereof'20179,292,465'Dynamic link width adjustment'20169,280,194'Dynamic link width modulation'20169,195,404'Exposing protected memory addresses'20158,935,578'Method and apparatus for optimizing power and latency on a link'20158,719,606'Optimizing performance and power consumption during memory power down state'20148,661,284'Method and system to improve the operations of a registered memory module'20148,438,410'Memory power management via dynamic memory operation states'20138,429,367'Systems, methods and apparatuses for clock enable (CKE) coordination'20138,375,241'Method and system to improve the operations of a registered memory module'20138,327,222'Mechanism for adjacent-symbol error correction and detection'20127,941,618'Fully buffered DIMM read data substitution for write acknowledgement'20117,885,914'Systems, methods and apparatuses for rank coordination'20117,865,753'Resource power controller to return a resource to an up state based on an estimate of a size of a gap in data traffic'20117,804,733'System and method for memory phase shedding'20107,734,980'Mitigating silent data corruption in a buffered memory module architecture'20107,644,347'Silent data corruption mitigation using error correction code with embedded signaling fault detection'20107,587,625'Memory replay mechanism'20097,516,349'Synchronized memory channels with unidirectional links'20097,509,560'Mechanism for adjacent-symbol error correction and detection'20097,444,479'Fully buffered DIMM read data substitution for write acknowledgement'20087,200,787'Memory channel utilizing permuting status patterns'20076,615,379'Method and apparatus for testing a logic device'20036,540,123'Pickup truck bed extender apparatus'20036,513,688'Pickup truck bed extender apparatus'20035,758,059'In-circuit emulator in which abrupt and deferred arming and disarming of several events on a microprocessor chip are controlled using a single-input pin'19985,513,338'Apparatus for tracing activity on a bus of an in-circuit emulator'19965,497,456'Apparatus for transferring information between an interrupt producer and an interrupt service environment'19965,434,804'Method and apparatus for synchronizing a JTAG test control signal to an on-chip clock signal'19955,392,186'Providing various electrical protections to a CMOS integrated circuit'19955,383,192'Minimizing the likelihood of slip between the instant a candidate for a break event is generated and the instant a microprocessor is instructed to perform a break, without missing breakpoints'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2020Patents assigned to INTEL CORP (36)· patent assignee history
1995–2020Based in Hillsboro, OR, US· patent location history
1998Based in Portland, OR, US· patent location history
2003Based in Birmingham, MI, US· patent location history
2007–2011Based in Aloha, OR, US· patent location history
2008–2016Patents assigned to ALEXANDER JAMES W (10)· patent assignee history
2013–2016Patents assigned to BODAS DEVADATTA V (4)· patent assignee history
2013–2014Patents assigned to DAVID HOWARD S (3)· patent assignee history
2013–2014Patents assigned to BAINS KULJIT S (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 36 | 1995–2020 |
| ALEXANDER JAMES Wself | 10 | 2008–2016 |
| BODAS DEVADATTA V | 4 | 2013–2016 |
| DAVID HOWARD S | 3 | 2013–2014 |
| BAINS KULJIT S | 2 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hillsboro, OR, US | 28 | 1995–2020 |
| Aloha, OR, US | 8 | 2007–2011 |
| Birmingham, MI, US | 2 | 2003 |
| Portland, OR, US | 1 | 1998 |