Inventor
Xiaoqian Zhang
Inventor
Shanghai, CN
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing15%
G11CStatic stores13%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses10%
G09GArrangements or circuits for control of indicating devices using static means to present variable information8%
H03KPulse technique8%
H04LTransmission of digital information, e.g. telegraphic communication8%
G06NComputing arrangements based on specific computational models5%
G06VImage or video recognition or understanding5%
H04NPictorial communication, e.g. television5%
A61BDiagnosis3%
PatentTitleYear
10,939,892Collimator, radiation emitting assembly and inspection apparatus202110,673,438Digital signal processing block202010,346,093Memory arrangement for tensor data20199,896,474'(3A,9B,10A,13A,14B,17A,20S,22E)-ergosta-5,7,22-trien-3-ol and methods of preparing and using the same'20189,779,786'Tensor operations and acceleration'20179,460,007'Programmable hardware blocks for time-sharing arithmetic units using memory mapping of periodic functions'20169,355,696'Calibration in a control device receiving from a source synchronous interface'20169,331,701'Receivers and methods of enabling the calibration of circuits receiving input data'20168,861,669'Stream clock recovery in high definition multimedia digital system'20148,531,352'Dynamic EDID generation'20138,422,518'Managing transmit jitter for multi-format digital audio transmission'20138,217,689'Method and circuit for DisplayPort video clock recovery'20128,095,707'Method for synchronization of peripherals with a central processing unit in an embedded system'20128,023,594'Asynchronous biphase mark signal receivers and methods of operating same'20117,940,662'Method and apparatus for forwarding bursty data'20117,750,696'Phase-locked loop'20107,573,896'Method and apparatus for generic interface, packet cut-through, overbooking, queue concatenation, and logical identification priority for a system packet interface device'20097,571,337'Integrated circuits and methods with transmit-side data bus deskew'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009–2013Patents assigned to INTEGRATED DEVICE TECH (8)· patent assignee history
2009–2014Based in Shanghai, CN· patent location history
2012–2014Patents assigned to ZHANG XIAOQIAN (5)· patent assignee history
2012–2013Patents assigned to GUAN ZHIYONG (2)· patent assignee history
2012–2013Patents assigned to LI QI (2)· patent assignee history
2016–2020Patents assigned to XILINX INC (6)· patent assignee history
2016–2020Based in San Jose, CA, US· patent location history
2018Based in Tianjin, CN· patent location history
2021Based in Beijing, CN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEGRATED DEVICE TECH | 8 | 2009–2013 |
| XILINX INC | 6 | 2016–2020 |
| ZHANG XIAOQIANself | 5 | 2012–2014 |
| GUAN ZHIYONG | 2 | 2012–2013 |
| LI QI | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Shanghai, CN | 10 | 2009–2014 |
| San Jose, California, US | 6 | 2016–2020 |
| Beijing, CN | 1 | 2021 |
| Tianjin, CN | 1 | 2018 |