LexDanaLexDanabeta
Inventor

Navneet Kaushik

Inventor
Delhi, IN

Overview

6→
Patents
2014–2019
Patent span
Physics
Primary field (CPC G)

Patents· 6 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing50%
G11CStatic stores40%
G01RMeasuring electric variables10%
PatentTitleYear
10,192,013Test logic at register transfer level in an integrated circuit design201910,095,822Memory built-in self-test logic in an integrated circuit design20189,865,362'Method and apparatus for testing error correction code (ECC) logic and physical memory onboard a manufactured integrated circuit (IC)'20189,640,280'Power domain aware insertion methods and designs for testing and repairing memory'20178,990,749'Method and apparatus for optimizing memory-built-in-self test'20158,719,761'Method and apparatus for optimizing memory-built-in-self test'2014

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2014–2019Patents assigned to CADENCE DESIGN SYSTEMS INC (6)· patent assignee history
2014–2015Patents assigned to ARORA PUNEET (2)· patent assignee history
2014–2015Patents assigned to CARD NORMAN (2)· patent assignee history
2014–2015Patents assigned to GREGOR STEVEN (2)· patent assignee history
2014–2015Patents assigned to KAUSHIK NAVNEET (2)· patent assignee history
2014Based in Padam Nagar, IN· patent location history
2015–2019Based in Delhi, IN· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
CADENCE DESIGN SYSTEMS INC62014–2019
ARORA PUNEET22014–2015
CARD NORMAN22014–2015
GREGOR STEVEN22014–2015
KAUSHIK NAVNEETself22014–2015
Locations
LocationPatentsSpan
Delhi, IN52015–2019
Padam Nagar, IN12014