Inventor

Joseph Fjelstad

Inventor

Maple Valley, WA, US

Overview

1984–2019

Patent span

Electricity

Primary field (CPC H)

Patents· 187 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1035%

H05KPrinted circuits20%

Y10TTechnical subjects covered by former us classification14%

H01RElectrically-conductive connections8%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%

G01RMeasuring electric variables4%

Y02PClimate change mitigation technologies in the production or processing of goods4%

LOC212%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%

H01PWaveguides1%

PatentTitleYear

10,517,174Solder alloy free electronic (SAFE) rigid-flexible/stretchable circuit assemblies having integral, conductive and heat spreading sections and methods for their manufacture2019 10,285,270Solder alloy free electronic (safe) rigid-flexible/stretchable circuit assemblies having integral, conductive and heat spreading sections and methods for their manufacture2019 D0828453Backgammon board2018 9,894,771'Occam process for components having variations in part dimensions'2018 D0806175Ellipsoid based gaming die having five flatted surfaces2017 D0801439'Ellipsoidal gaming die having five flatted surfaces'2017 D0801438'Ellipsoidal gaming die having three flatted surfaces'2017 9,681,550'Method of making a circuit subassembly'2017 D0774144'Sphere based game die having 20 flatted surfaces'2016 D0772989'Holder for irregularly shaped dice'2016 D0771750'Sphere based die having 6 flatted surfaces'2016 8,796,830'Stackable low-profile lead frame package'2014 8,598,696'Multi-surface IC packaging structures'2013 8,558,386'Methods of making compliant semiconductor chip packages'2013 8,510,935'Electronic assemblies without solder and methods for their manufacture'2013 8,513,799'Method of electrically connecting a microelectronic component'2013 8,482,110'Electronic assemblies without solder and methods for their manufacture'2013 8,404,977'Flexible circuit assembly without solder'2013 8,338,713'Cabled signaling system and components thereof'2012 8,338,925'Microelectronic assemblies having compliant layers'2012 8,333,617'Connector constructions for electronic applications'2012 8,324,727'Low profile discrete electronic components and applications of same'2012 8,313,333'Connector having a housing with a conductor with a ramp section and a curved surface section'2012 8,300,425'Electronic assemblies without solder having overlapping components'2012 8,246,387'Connector constructions for electronic applications'2012 8,199,450'ESD protection utilizing radiated thermal relief'2012 8,193,042'Flexible circuit assemblies without solder and methods for their manufacture'2012 RE043404'Methods for providing void-free layer for semiconductor assemblies'2012 8,148,205'Method of electrically connecting a microelectronic component'2012 8,148,199'Method of electrically connecting a microelectronic component'2012 8,114,711'Method of electrically connecting a microelectronic component'2012 8,093,712'Monolithic molded flexible electronic assemblies without solder and methods for their manufacture'2012 8,079,848'Electrical connector with conductors with a ramp to induce torsion'2011 8,080,874'Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween'2011 8,067,777'Light emitting diode package assembly'2011 8,047,855'High speed, direct path, stair-step, electronic connectors with improved signal integrity characteristics and methods for their manufacture'2011 8,026,600'Controlled impedance structures for high density interconnections'2011 7,989,929'Direct-connect signaling system'2011 7,981,703'Electronic assemblies without solder and methods for their manufacture'2011 7,973,391'Tapered dielectric and conductor structures and applications thereof'2011 7,948,093'Memory IC package assembly having stair step metal layer and apertures'2011 7,943,434'Monolithic molded flexible electronic assemblies without solder and methods for their manufacture'2011 7,926,173'Method of making a circuit assembly'2011 7,919,355'Multi-surface IC packaging structures and methods for their manufacture'2011 7,909,615'Torsionally-induced contact-force conductors for electrical connector systems'2011 7,872,344'Microelectronic assemblies having compliant layers'2011 7,845,986'Torsionally-induced contact-force conductors for electrical connector systems'2010 7,837,477'Electrical interconnection devices incorporating Fedundant contact points for reducing capacitive stubs and improved signal integrity'2010 7,750,446'IC package structures having separate circuit interconnection structures and assemblies constructed thereof'2010 7,737,545'Multi-surface IC packaging structures and methods for their manufacture'2010 7,732,904'Multi-surface contact IC packaging structures and assemblies'2010 7,701,323'Low profile discrete electronic components and applications of same'2010 7,651,382'Electrical interconnection devices incorporating redundant contact points for reducing capacitive stubs and improved signal integrity'2010 7,651,336'High speed, direct path, stair-step, electronic connectors with improved signal integrity characteristics and methods for their manufacture'2010 7,652,381'Interconnect system without through-holes'2010 7,613,011'Signal-segregating connector system'2009 7,531,894'Method of electrically connecting a microelectronic component'2009 7,528,008'Method of electrically connecting a microelectronic component'2009 7,466,021'Memory packages having stair step interconnection layers'2008 7,408,260'Microelectronic assemblies having compliant layers'2008 7,404,746'Electrical interconnection devices incorporating redundant contact points for reducing capacitive stubs and improved signal integrity'2008 7,388,279'Tapered dielectric and conductor structures and applications thereof'2008 7,310,239'IC packaging interposer having controlled impedance or optical interconnections and an integral heat spreader'2007 7,307,293'Direct-connect integrated circuit signaling system for bypassing intra-substrate printed circuit signal paths'2007 7,278,855'High speed, direct path, stair-step, electronic connectors with improved signal integrity characteristics and methods for their manufacture'2007 7,279,783'Partitioned integrated circuit package with central clock driver'2007 7,280,372'Stair step printed circuit board structures for high speed signal transmissions'2007 7,276,400'Methods of making microelectronic packages with conductive elastomeric posts'2007 7,227,759'Signal-segregating connector system'2007 7,205,613'Insulating substrate for IC packages having integral ESD protection'2007 7,192,320'Electrical interconnection devices incorporating redundant contact points for reducing capacitive stubs and improved signal integrity'2007 7,176,580'Structures and methods for wire bonding over active, brittle and low K dielectric areas of an IC chip'2007 7,165,316'Methods for manufacturing resistors using a sacrificial layer'2007 7,138,299'Method of electrically connecting a microelectronic component'2006 7,112,879'Microelectronic assemblies having compliant layers'2006 7,095,054'Semiconductor package having light sensitive chips'2006 7,091,820'Methods for manufacturing resistors using a sacrificial layer'2006 7,067,742'Connection component with peelable leads'2006 7,061,096'Multi-surface IC packaging structures and methods for their manufacture'2006 7,049,929'Resistor process'2006 7,014,472'System for making high-speed connections to board-mounted modules'2006 6,978,538'Method for making a microelectronic interposer'2005 6,972,495'Compliant package with conductive elastomeric posts'2005 6,938,338'Method of making an electronic contact'2005 6,933,610'Method of bonding a semiconductor die without an ESD circuit and a separate ESD circuit to an external lead, and a semiconductor device made thereby'2005 6,906,422'Microelectronic elements with deformable leads'2005 6,891,272'Multi-path via interconnection structures and methods for manufacturing the same'2005 6,888,168'Semiconductor package having light sensitive chips'2005 6,884,120'Array connector with deflectable coupling structure for mating with other components'2005 6,885,106'Stacked microelectronic assemblies and methods of making same'2005 6,876,212'Methods and structures for electronic probing arrays'2005 6,856,235'Methods for manufacturing resistors using a sacrificial layer'2005 6,848,173'Microelectric packages having deformed bonded leads and methods therefor'2005 6,847,101'Microelectronic package having a compliant layer with bumped protrusions'2005 6,847,107'Image forming apparatus with improved transfer efficiency'2005 6,826,827'Forming conductive posts by selective removal of conductive material'2004 6,821,815'Method of assembling a semiconductor chip package'2004 6,821,821'Methods for manufacturing resistors using a sacrificial layer'2004 6,809,608'Transmission line structure with an air dielectric'2004 6,780,747'Methods for providing void-free layers for semiconductor assemblies'2004 6,774,317'Connection components with posts'2004 6,737,265'Microelectronic unit forming methods and materials'2004 6,709,899'Methods of making microelectronic assemblies having conductive elastomeric posts'2004 6,706,973'Electrical connection with inwardly deformable contacts'2004 6,700,072'Electrical connection with inwardly deformable contacts'2004 6,690,186'Methods and structures for electronic probing arrays'2004 6,653,172'Methods for providing void-free layers for semiconductor assemblies'2003 6,635,514'Compliant package with conductive elastomeric posts'2003 6,586,955'Methods and structures for electronic probing arrays'2003 6,583,444'Semiconductor packages having light-sensitive chips'2003 6,573,609'Microelectronic component with rigid interposer'2003 6,541,845'Components with releasable leads and methods of making releasable leads'2003 6,541,867'Microelectronic connector with planar elastomer sockets'2003 6,518,160'Method of manufacturing connection components using a plasma patterned mask'2003 6,518,662'Method of assembling a semiconductor chip package'2003 6,499,216'Methods and structures for electronic probing arrays'2002 6,486,003'Expandable interposer for a microelectronic package and method therefor'2002 6,486,547'Microelectronic assembly incorporating lead regions defined by gaps in a polymeric sheet'2002 6,468,836'Laterally situated stress/strain relieving lead for a semiconductor chip package'2002 6,465,878'Compliant microelectronic assemblies'2002 6,465,747'Microelectronic assemblies having solder-wettable pads and conductive elements'2002 6,458,681'Method for providing void free layer for semiconductor assemblies'2002 6,417,029'Compliant package with conductive elastomeric posts'2002 6,373,128'Semiconductor assemblies with reinforced peripheral regions'2002 6,361,959'Microelectronic unit forming methods and materials'2002 6,357,112'Method of making connection component'2002 6,329,607'Microelectronic lead structures with dielectric layers'2001 6,324,754'Method for fabricating microelectronic assemblies'2001 6,317,974'Methods for creating wear resistant contact edges'2001 6,307,260'Microelectronic assembly fabrication with terminal formation from a conductive layer'2001 6,294,830'Microelectronic assembly with conductive terminals having an exposed surface through a dielectric layer'2001 6,284,563'Method of making compliant microelectronic assemblies'2001 6,274,820'Electrical connections with deformable contacts'2001 6,266,872'Method for making a connection component for a semiconductor chip package'2001 6,266,874'Methods of making microelectronic components having electrophoretically deposited layers'2001 6,265,759'Laterally situated stress/strain relieving lead for a semiconductor chip package'2001 6,261,863'Components with releasable leads and methods of making releasable leads'2001 6,253,992'Solder ball placement fixtures and methods'2001 6,247,228'Electrical connection with inwardly deformable contacts'2001 6,239,384'Microelectric lead structures with plural conductors'2001 6,239,386'Electrical connections with deformable contacts'2001 6,229,100'Low profile socket for microelectronic components and method for making the same'2001 6,228,686'Method of fabricating a microelectronic assembly using sheets with gaps to define lead regions'2001 6,221,750'Fabrication of deformable leads of microelectronic elements'2001 6,218,213'Microelectronic components with frangible lead sections'2001 6,211,690'Apparatus for electrically testing bare printed circuits'2001 6,211,572'Semiconductor chip package with fan-in leads'2001 6,205,660'Method of making an electronic contact'2001 6,208,025'Microelectronic component with rigid interposer'2001 6,204,091'Method of assembling a semiconductor chip package'2001 6,196,042'Coining tool and process of manufacturing same for making connection components'2001 6,177,636'Connection components with posts'2001 6,157,075'Semiconductor assemblies with reinforced peripheral regions'2000 6,133,072'Microelectronic connector with planar elastomer sockets'2000 6,130,116'Method of encapsulating a microelectronic assembly utilizing a barrier'2000 6,107,123'Methods for providing void-free layers for semiconductor assemblies'2000 6,107,682'Compliant wirebond packages having wire loop'2000 6,093,584'Method for encapsulating a semiconductor package having apertures through a sacrificial layer and contact pads'2000 6,086,386'Flexible connectors for microelectronic elements'2000 6,007,349'Flexible contact post and post socket and associated methods therefor'1999 6,001,671'Methods for manufacturing a semiconductor package having a sacrificial layer'1999 6,002,168'Microelectronic component with rigid interposer'1999 5,989,939'Process of manufacturing compliant wirebond packages'1999 5,989,936'Microelectronic assembly fabrication with terminal formation from a conductive layer'1999 5,983,492'Low profile socket for microelectronic components and method for making the same'1999 5,980,270'Soldering with resilient contacts'1999 5,966,587'Methods of making semiconductor assemblies with reinforced peripheral regions'1999 5,934,914'Microelectronic contacts with asperities and methods of making same'1999 5,904,498'Connection component with releasable leads'1999 5,834,339'Methods for providing void-free layers for semiconductor assemblies'1998 5,821,608'Laterally situated stress/strain relieving lead for a semiconductor chip package'1998 5,821,609'Semiconductor connection component with frangible lead sections'1998 5,812,378'Microelectronic connector for engaging bump leads'1998 5,807,453'Fabrication of leads on semiconductor connection components'1998 5,802,699'Methods of assembling microelectronic assembly with socket for engaging bump leads'1998 5,776,796'Method of encapsulating a semiconductor package'1998 5,777,379'Semiconductor assemblies with reinforced peripheral regions'1998 5,763,941'Connection component with releasable leads'1998 5,679,194'Fabrication of leads on semiconductor connection components'1997 5,632,631'Microelectronic contacts with asperities and methods of making same'1997 5,629,239'Manufacture of semiconductor connection components with frangible lead sections'1997 5,615,824'Soldering with resilient contacts'1997 5,597,470'Method for making a flexible lead for a microelectronic device'1997 5,590,460'Method of making multilayer circuit'1997 D0345182'Irregularly shaped dice'1994 5,250,758'Methods and systems of preparing extended length flexible harnesses'1993 4,482,445'Methods and apparatus for electrochemically deburring perforate metallic clad dielectric laminates'1984

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1994–2019Patents assigned to FJELSTAD JOSEPH (10)· patent assignee history

1997–2013Patents assigned to TESSERA INC (118)· patent assignee history

1997–2011Based in Sunnyvale, CA, US· patent location history

2003–2019Based in Maple Valley, WA, US· patent location history

2004Based in Sunnvale, CA, US· patent location history

2008–2012Patents assigned to INTERCONNECT PORTFOLIO LLC (16)· patent assignee history

2010–2013Patents assigned to SAMSUNG ELECTRONICS CO LTD (10)· patent assignee history

2011–2017Patents assigned to FJELSTAD JOSEPH C (18)· patent assignee history

2016–2019Based in North Bend, WA, US· patent location history

2016Based in New Bend, WA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TESSERA INC	118	1997–2013
FJELSTAD JOSEPH Cself	18	2011–2017
INTERCONNECT PORTFOLIO LLC	16	2008–2012
FJELSTAD JOSEPHself	10	1994–2019
SAMSUNG ELECTRONICS CO LTD	10	2010–2013

Locations

Location	Patents	Span
Maple Valley, Washington, US	93	2003–2019
Sunnyvale, California, US	82	1997–2011
North Bend, Washington, US	7	2016–2019
New Bend, Washington, US	1	2016
Sunnvale, California, US	1	2004