Inventor
Gordon J. Brebner
Inventor
San Jose, CA, US
Overview
Patents· 43 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing42%
H04LTransmission of digital information, e.g. telegraphic communication42%
H03KPulse technique4%
A63BApparatus for physical training, gymnastics, swimming, climbing, or fencing2%
G05BControl or regulating systems in general2%
H01LSemiconductor devices2%
H03MCoding2%
H04WWireless communication networks2%
H10DInorganic electric semiconductor devices2%
PatentTitleYear
10,834,241Streaming editor circuit for implementing a packet deparsing process20209,674,081'Efficient mapping of table pipelines for software-defined networking (SDN) data plane'20179,350,385'Modular and scalable cyclic redundancy check computation circuit'20169,270,517'Tuple construction from data packets'20169,110,524'High throughput finite state machine'20158,874,837'Embedded memory and dedicated processor structure within an integrated circuit'20148,780,914'Parallel processing of network packets'20148,775,685'Parallel processing of network packets'20148,560,996'Method and system for preparing modularized circuit designs for dynamic partial reconfiguration of programmable logic'20138,443,102'Pipeline of a packet processor programmed to extract packet fields'20138,385,340'Pipeline of a packet processor programmed to concurrently perform operations'20138,358,653'Generating a pipeline of a packet processor from a parsing tree'20138,311,057'Managing formatting of packets of a communication protocol'20128,266,583'Flexible packet data storage for diverse packet processing applications'20128,160,092'Transforming a declarative description of a packet processor'20128,144,702'Generation of a pipeline for processing a type of network packets'20128,121,826'Graphical user interface for system design'20128,065,130'Method for message processing on a programmable logic device'20118,015,386'Configurable memory manager'20117,949,790'Machines for inserting or removing fixed length data at a fixed location in a serial data stream'20117,949,007'Methods of clustering actions for manipulating packets of a communication protocol'20117,949,793'Method and apparatus for providing an interface between a programmable circuit and a processor'20117,852,117'Hierarchical interface for IC system'20107,839,849'Formatting fields of communication packets'20107,822,066'Processing variable size fields of the packets of a communication protocol'20107,817,657'Circuit for processing network packets'20107,804,844'Dataflow pipeline implementing actions for manipulating packets of a communication protocol'20107,784,014'Generation of a specification of a network packet processor'20107,770,179'Method and apparatus for multithreading on a programmable logic device'20107,669,166'Generation of a specification of a processor of network packets'20107,636,909'Automatically generating multithreaded datapaths'20097,636,908'Generation of a specification of a network packet processor'20097,574,680'Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip'20097,552,042'Method for message processing on a programmable logic device'20097,454,587'Method and apparatus for memory management in an integrated circuit'20087,398,502'Micro-coded processors for concurrent processing in a programmable logic device'20087,379,451'Address lookup table'20087,281,093'Memory apparatus for a message processing system and method of providing same'20077,228,520'Method and apparatus for a programmable interface of a soft platform on a programmable logic device'20077,185,309'Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip'20076,891,397'Gigabit router on a single programmable logic device'20056,794,896'Method and apparatus for multithreading'20044,650,184'Ski exerciser apparatus'1987Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1987Patents assigned to BREBNER GORDON (1)· patent assignee history
2004–2020Patents assigned to XILINX INC (42)· patent assignee history
2004–2020Based in Monte Sereno, CA, US· patent location history
2007Based in Campbell, CA, US· patent location history
2008–2012Based in Los Gatos, CA, US· patent location history
2010–2016Based in San Jose, CA, US· patent location history
2011–2014Patents assigned to BREBNER GORDON J (13)· patent assignee history
2012–2013Patents assigned to ATTIG MICHAEL E (6)· patent assignee history
2012–2014Patents assigned to NEELY CHRISTOPHER E (3)· patent assignee history
2015Based in Wrightington, GB· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| XILINX INC | 42 | 2004–2020 |
| BREBNER GORDON Jself | 13 | 2011–2014 |
| ATTIG MICHAEL E | 6 | 2012–2013 |
| NEELY CHRISTOPHER E | 3 | 2012–2014 |
| BREBNER GORDONself | 1 | 1987 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 21 | 2010–2016 |
| Los Gatos, California, US | 10 | 2008–2012 |
| Monte Sereno, California, US | 9 | 2004–2020 |
| Wrightington, GB | 1 | 2015 |
| Campbell, California, US | 1 | 2007 |