Inventor
Makarem A. Hussein
Inventor
Beaverton, OR, US
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1038%
H10DInorganic electric semiconductor devices17%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices9%
H10BElectronic memory devices6%
C08LCompositions of macromolecular compounds4%
C09DCoating compositions, e.g. paints, varnishes or lacquers4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
C11DDetergent compositions2%
F25BRefrigeration machines, plants or systems2%
PatentTitleYear
8,992,806'Antireflective coatings for via fill and photolithography applications and methods of preparation thereof'20158,394,701'Dielectric spacers for metal interconnects and method to form the same'20138,053,159'Antireflective coatings for via fill and photolithography applications and methods of preparation thereof'20117,923,760'Dielectric spacers for metal interconnects and method to form the same'20117,659,196'Soluble hard mask for interlayer dielectric patterning'20107,649,239'Dielectric spacers for metal interconnects and method to form the same'20107,442,675'Cleaning composition and method of cleaning semiconductor substrate'20087,326,981'Methods and apparatuses for producing a polymer memory device'20087,166,922'Continuous metal interconnects'20077,157,380'Damascene process for fabricating interconnect layers in an integrated circuit'20077,078,754'Methods and apparatuses for producing a polymer memory device'20067,071,554'Stress mitigation layer to reduce under bump stress concentration'20067,008,872'Use of conductive electrolessly deposited etch stop layers, liner layers and via plugs in interconnect structures'20066,981,380'Thermoelectric cooling for microelectronic packages and dice'20066,958,547'Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugs'20056,908,829'Method of forming an air gap intermetal layer dielectric (ILD) by utilizing a dielectric material to bridge underlying metal lines'20056,900,063'Methods and apparatuses for producing a polymer memory device'20056,774,037'Method integrating polymeric interlayer dielectric in integrated circuits'20046,720,631'Transistor having a deposited dual-layer spacer structure'20046,649,515'Photoimageable material patterning techniques useful in fabricating conductive lines in circuit structures'20036,406,995'Pattern-sensitive deposition for damascene processing'20026,384,481'Single step electroplating process for interconnect via fill and metal line patterning'20026,365,529'Method for patterning dual damascene interconnects using a sacrificial light absorbing material'20026,329,118'Method for patterning dual damascene interconnects using a sacrificial light absorbing material'20016,169,024'Process to manufacture continuous metal interconnects'20016,037,255'Method for making integrated circuit having polymer interlayer dielectric'20006,020,266'Single step electroplating process for interconnect via fill and metal line patterning'20005,714,413'Method of making a transistor having a deposited dual-layer spacer structure'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2013Patents assigned to INTEL CORP (26)· patent assignee history
1998–2015Based in Beaverton, OR, US· patent location history
2011–2015Patents assigned to HONEYWELL INT INC (2)· patent assignee history
2013–2015Patents assigned to HUSSEIN MAKAREM A (2)· patent assignee history
2013Patents assigned to BOYANOV BOYAN (1)· patent assignee history
2015Patents assigned to FRADKIN MARK A (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 26 | 1998–2013 |
| HONEYWELL INT INC | 2 | 2011–2015 |
| HUSSEIN MAKAREM Aself | 2 | 2013–2015 |
| BOYANOV BOYAN | 1 | 2013 |
| FRADKIN MARK A | 1 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Beaverton, OR, US | 28 | 1998–2015 |