Inventor
Kai Frohberg
Inventor
Niederau, DE
Overview
Patents· 90 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices34%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1029%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1022%
H01LSemiconductor devices8%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
H10BElectronic memory devices1%
C23CCoating metallic material1%
G02BOptical elements, systems or apparatus1%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
H01SDevices using the process of light amplification by stimulated emission of radiation [laser] to amplify or generate light1%
PatentTitleYear
9,761,689'Method of forming a semiconductor device and according semiconductor device'20179,590,056'Semiconductor device comprising contact structures with protection layers formed on sidewalls of contact etch stop layers'20179,269,809'Methods for forming protection layers on sidewalls of contact etch stop layers'20169,245,860'Metallization system of a semiconductor device including metal pillars having a reduced diameter at the bottom'20169,196,684'Tensile nitride profile shaper etch to provide void free gapfill'20159,159,661'Integrated circuits with close electrical contacts and methods for fabricating the same'20159,153,684'Semiconductor fuses in a semiconductor device comprising metal gates'20159,006,114'Method for selectively removing a spacer in a dual stress liner approach'20158,941,182'Buried sublevel metallizations for improved transistor density'20158,883,582'High-K gate electrode structure formed after transistor fabrication by using a spacer'20148,877,597'Embedding metal silicide contact regions reliably into highly doped drain and source regions by a stop implantation'20148,859,398'Enhancing adhesion of interlayer dielectric materials of semiconductor devices by suppressing silicide formation at the substrate edge'20148,859,418'Methods of forming conductive structures using a dual metal hard mask technique'20148,835,303'Metallization system of a semiconductor device comprising extra-tapered transition vias'20148,828,887'Restricted stress regions formed in the contact level of a semiconductor device'20148,786,088'Semiconductor device including ultra low-K (ULK) metallization stacks with reduced chip-package interaction'20148,772,178'Technique for forming a dielectric interlayer above a structure including closely spaced lines'20148,735,237'Method for increasing penetration depth of drain and source implantation species for a given gate height'20148,722,511'Reduced topography in isolation regions of a semiconductor device by applying a deposition/etch sequence prior to forming the interlayer dielectric'20148,673,696'SOI semiconductor device comprising a substrate diode with reduced metal silicide leakage'20148,658,494'Dual contact metallization including electroless plating in a semiconductor device'20148,615,145'Semiconductor device comprising a buried waveguide for device internal optical communication'20138,609,524'Method for making semiconductor device comprising replacement gate electrode structures with an enhanced diffusion barrier'20138,580,684'Contact elements of semiconductor devices comprising a continuous transition to metal lines of a metallization layer'20138,536,050'Selective shrinkage of contact elements in a semiconductor device'20138,536,052'Semiconductor device comprising contact elements with silicided sidewall regions'20138,492,269'Hybrid contact structure with low aspect ratio contacts in a semiconductor device'20138,492,217'Methods of forming conductive contacts with reduced dimensions'20138,470,661'High-K gate electrode structure formed after transistor fabrication by using a spacer'20138,440,534'Threshold adjustment for MOS devices by adapting a spacer width prior to implantation'20138,436,425'SOI semiconductor device comprising substrate diodes having a topography tolerant contact structure'20138,384,161'Contact optimization for enhancing stress transfer in closely spaced transistors'20138,377,820'Method of forming a metallization system of a semiconductor device by using a hard mask for defining the via size'20138,368,221'Hybrid contact structure with low aspect ratio contacts in a semiconductor device'20138,367,504'Method for forming semiconductor fuses in a semiconductor device comprising metal gates'20138,361,844'Method for adjusting the height of a gate electrode in a semiconductor device'20138,357,610'Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectrics'20138,349,744'Double deposition of a stress-inducing layer in an interlayer dielectric with intermediate stress relaxation in a semiconductor device'20138,338,284'Stress engineering in a contact level of semiconductor devices by stressed conductive layers and an isolation spacer'20128,318,598'Contacts and vias of a semiconductor device formed by a hard mask and double exposure'20128,241,973'Method for increasing penetration depth of drain and source implantation species for a given gate height'20128,216,927'Method of reducing contamination by providing a removable polymer protection film during microstructure processing'20128,198,147'Superior fill conditions in a replacement gate approach by using a tensile stressed overlayer'20128,129,276'Void sealing in a dielectric material of a contact level of a semiconductor device comprising closely spaced transistors'20128,110,487'Method of creating a strained channel region in a transistor by deep implantation of strain-inducing species below the channel region'20128,105,962'Method and a semiconductor device comprising a protection layer for reducing stress relaxation in a dual stress liner approach'20128,101,524'Technique for enhancing the fill capabilities in an electrochemical deposition process by edge rounding of trenches'20128,048,726'SOI semiconductor device with reduced topography above a substrate window area'20118,048,736'Semiconductor device comprising a capacitor in the metallization system and a method of forming the capacitor'20118,040,497'Method and test structure for estimating focus settings in a lithography process based on CD measurements'20118,030,209'Enhancing structural integrity of low-k dielectrics in metallization systems of semiconductor devices by using a crack suppressing material layer'20118,017,504'Transistor having a high-k metal gate stack and a compressively stressed channel'20117,998,823'Method for reducing leakage currents caused by misalignment of a contact structure by increasing an error tolerance of the contact patterning process'20117,989,352'Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics'20117,977,237'Fabricating vias of different size of a semiconductor device by splitting the via patterning process'20117,955,962'Method of reducing contamination by providing a removable polymer protection film during microstructure processing'20117,932,166'Field effect transistor having a stressed contact etch stop layer with reduced conformality'20117,910,496'Technique for forming an interlayer dielectric material of increased reliability above a structure including closely spaced lines'20117,906,815'Increased reliability for a contact structure to connect an active region with a polysilicon line'20117,902,581'Semiconductor device comprising a contact structure based on copper and tungsten'20117,871,941'Method for reducing resist poisoning during patterning of stressed nitrogen-containing layers in a semiconductor device'20117,871,877'Technique for strain engineering in silicon-based transistors by using implantation techniques for forming a strain-inducing layer under the channel region'20117,838,354'Method for patterning contact etch stop layers by using a planarization process'20107,838,359'Technique for forming contact insulation layers and silicide regions with different characteristics'20107,833,874'Technique for forming an isolation trench as a stress source for strain engineering'20107,800,106'Test structure for OPC-related shorts between lines in a semiconductor device'20107,763,476'Test structure for determining characteristics of semiconductor alloys in SOI transistors by x-ray diffraction'20107,763,532'Technique for forming a dielectric etch stop layer above a structure including closely spaced lines'20107,741,191'Method for preventing the formation of electrical shorts via contact ILD voids'20107,713,815'Semiconductor device including a vertical decoupling capacitor'20107,705,352'Test structure for estimating electromigration effects with increased robustness with respect to barrier defects in vias'20107,622,391'Method of forming an electrically conductive line in an integrated circuit'20097,608,501'Technique for creating different mechanical strain by forming a contact etch stop layer stack having differently modified intrinsic stress'20097,608,912'Technique for creating different mechanical strain in different CPU regions by forming an etch stop layer having differently modified intrinsic stress'20097,563,731'Field effect transistor having a stressed dielectric layer based on an enhanced device topography'20097,556,996'Field effect transistor comprising a stressed channel region and method of forming the same'20097,550,396'Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor device'20097,528,059'Method for reducing polish-induced damage in a contact structure by forming a capping layer'20097,517,816'Technique for creating different mechanical stress in different channel regions by forming an etch stop layer having differently modified intrinsic stress'20097,491,555'Method and semiconductor structure for monitoring the fabrication of interconnect structures and contacts in a semiconductor device'20097,482,219'Technique for creating different mechanical strain by a contact etch stop layer stack with an intermediate etch stop layer'20097,462,563'Method of forming an etch indicator layer for reducing etch non-uniformities'20087,442,638'Method for forming a tungsten interconnect structure with enhanced sidewall coverage of the barrier layer'20087,396,718'Technique for creating different mechanical strain in different channel regions by forming an etch stop layer stack having differently modified intrinsic stress'20087,381,602'Method of forming a field effect transistor comprising a stressed channel region'20087,341,903'Method of forming a field effect transistor having a stressed channel region'20087,314,793'Technique for controlling mechanical stress in a channel region by spacer removal'20087,314,824'Nitrogen-free ARC/capping layer and method of manufacturing the same'20087,279,415'Method for forming a metallization layer stack to reduce the roughness of metal lines'20077,259,091'Technique for forming a passivation layer prior to depositing a barrier layer in a copper metallization layer'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2016Patents assigned to ADVANCED MICRO DEVICES INC (43)· patent assignee history
2007–2014Based in Meissen, DE· patent location history
2008–2017Based in Niederau, DE· patent location history
2010–2017Patents assigned to GLOBALFOUNDRIES INC (46)· patent assignee history
2012–2016Patents assigned to FROHBERG KAI (40)· patent assignee history
2012–2016Patents assigned to FEUSTEL FRANK (14)· patent assignee history
2012–2016Patents assigned to WERNER THOMAS (11)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| GLOBALFOUNDRIES INC | 46 | 2010–2017 |
| ADVANCED MICRO DEVICES INC | 43 | 2007–2016 |
| FROHBERG KAIself | 40 | 2012–2016 |
| FEUSTEL FRANK | 14 | 2012–2016 |
| WERNER THOMAS | 11 | 2012–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Niederau, DE | 81 | 2008–2017 |
| Meissen, DE | 9 | 2007–2014 |