Inventor
ROY EDWARD MEADE
Inventor
US
Overview
Patents· 35 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G02Bprimary
G02BOptical elements, systems or apparatus30%
H04BTransmission13%
H01LSemiconductor devices12%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
H04JMultiplex communication5%
H04QSelecting4%
G01RMeasuring electric variables4%
G11CStatic stores4%
H01SDevices using the process of light amplification by stimulated emission of radiation [laser] to amplify or generate light4%
PatentTitleYear
12,567,910Pooled memory system enabled by monolithic in-package optical I/O202612,567,920Low-power optical input/output chiplet for ethernet switches (TeraPHYe)202612,512,402Chip-last wafer-level fan-out with optical fiber alignment structure202512,442,980Planar fiber shuffle202512,416,763Fiber attach enabled wafer level fanout202512,321,022Apparatus for optical fiber-to-photonic chip connection and associated methods202512,313,891Thermal management system for multi-chip-module and associated methods202512,092,880Beam steering structure with integrated polarization splitter202412,057,332Wafer-level etching methods for planar photonics circuits and devices202412,019,269Multi-chip packaging of silicon photonics202412,014,962Systems and methods for wafer-level photonic testing202411,994,724Chip-to-chip optical data communication system202411,916,602Remote memory architectures enabled by monolithic in-package optical i/o202411,899,251Vertical integrated photonics chiplet for in-package optical interconnect202411,867,944Photonic systems to enable top-side wafer-level optical and electrical test202411,823,990Chip-last wafer-level fan-out with optical fiber alignment structure202311,822,128Fiber attach enabled wafer level fanout202311,799,554Laser module for optical data communication system within silicon interposer202311,777,633Optical multiplexer/demultiplexer module and associated methods202311,705,972Pooled memory system enabled by monolithic in-package optical I/O202311,694,935Systems and methods for wafer-level photonic testing202311,563,506Electro-optical interface module and associated methods202311,500,153Multi-chip packaging of silicon photonics202211,493,708Thermal management system for multi-chip-module and associated methods202211,424,830Laser module for optical data communication system202211,405,125TORminator system and associated methods202211,394,465Laser module for optical data communication system within silicon interposer202211,280,970Beam steering structure with integrated polarization splitter202211,280,959Photonics systems to enable top-side wafer-level optical and electrical test202211,249,260Chip-to-chip optical data communication system202211,233,580Pooled DRAM system enabled by monolithic in-package optical I/O202211,233,596Optical multiplexer/demultiplexer module and associated methods202211,163,120Fiber attach enabled wafer level fanout202111,156,773Wafer-level handle replacement processing202111,137,548Retro reflector and associated methods2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to AYAR LABS INC (35)· patent assignee history
2021–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| AYAR LABS INC | 35 | 2021–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 35 | 2021–2026 |