Inventor

Gary W. Thome

Inventor

Tomball, TX, US

Overview

1993–2021

Patent span

Physics

Primary field (CPC G)

Patents· 49 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing88%

G11CStatic stores6%

G06TImage data processing or generation, in general2%

G10HElectrophonic musical instruments2%

H03HImpedance networks, e.g. resonant circuits2%

PatentTitleYear

11,100,000Embedded image management2021 9,003,091'Flow control for a Serial Peripheral Interface bus'2015 6,215,504'Line drawing using operand routing and operation selective multimedia extension unit'2001 6,154,831'Decoding operands for multimedia applications instruction coded with less number of bits than combination of register slots and selectable specific values'2000 6,115,791'Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence control'2000 6,061,521'Computer having multimedia operations executable as two distinct sets of operations within a single instruction cycle'2000 6,009,505'System and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slot'1999 5,991,865'MPEG motion compensation using operand routing and performing add and divide in a single instruction'1999 5,960,459'Memory controller having precharge prediction based on processor and PCI bus cycles'1999 5,938,739'Memory controller including write posting queues, bus read control logic, and a data contents counter'1999 5,931,892'Enhanced adaptive filtering technique'1999 5,918,023'System design to support either Pentium Pro processors, Pentium II processors, and future processor without having to replace the system board'1999 5,893,145'System and method for routing operands within partitions of a source register to partitions within a destination register'1999 5,892,964'Computer bridge interfaces for accelerated graphics port and peripheral component interconnect devices'1999 5,862,063'Enhanced wavetable processing technique on a vector processor having operand routing and slot selectable operations'1999 5,857,116'Circuit for disabling an address masking control signal when a microprocessor is in a system management mode'1999 5,848,267'Computer system speed control using memory refresh counter'1998 5,822,756'Microprocessor cache memory way prediction based on the way of a previous memory read'1998 5,819,105'System in which processor interface snoops first and second level caches in parallel with a memory access by a bus mastering device'1998 5,813,038'Memory controller having precharge prediction based on processor and PC bus cycles'1998 5,809,549'Burst SRAMs for use with a high speed clock'1998 5,778,413'Programmable memory controller having two level look-up for memory timing parameter'1998 5,778,433'Computer system including a first level write-back cache and a second level cache'1998 5,692,154'Circuit for masking a dirty status indication provided by a cache dirty memory under certain conditions so that a cache memory controller properly controls a cache tag memory'1997 5,664,225'Circuit for disabling an address masking control signal when a microprocessor is in a system management mode'1997 5,652,856'Memory controller having all DRAM address and control singals provided synchronously from a single device'1997 5,651,130'Memory controller that dynamically predicts page misses'1997 5,640,532'Microprocessor cache memory way prediction based on the way of previous memory read'1997 5,634,112'Memory controller having precharge prediction based on processor and PCI bus cycles'1997 5,634,073'System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation'1997 5,604,884'Burst SRAMS for use with a high speed clock'1997 5,596,741'Computer system which overrides write protection status during execution in system management mode'1997 5,586,286'Memory controller having flip-flops for synchronously generating DRAM address and control signals from a single chip'1996 5,581,727'Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence control'1996 5,579,512'Systempro emulation in a symmetric multiprocessing computer system'1996 5,537,555'Fully pipelined and highly concurrent memory controller'1996 5,524,235'System for arbitrating access to memory with dynamic priority assignment'1996 5,509,139'Circuit for disabling an address masking control signal using OR gate when a microprocessor is in a system management mode'1996 5,509,138'Method for determining speeds of memory modules'1996 5,475,829'Computer system which overrides write protection status during execution in system management mode'1995 5,454,081'Expansion bus type determination apparatus'1995 5,440,751'Burst data transfer to single cycle data transfer conversion and strobe signal conversion'1995 5,423,021'Auxiliary control signal decode using high performance address lines'1995 5,408,636'System for flushing first and second caches upon detection of a write operation to write protected areas'1995 5,404,559'Apparatus for asserting an end of cycle signal to a processor bus in a computer system if a special cycle is detected on the processor bus without taking action on the special cycle'1995 5,353,423'Memory controller for use with write-back cache system and multiple bus masters coupled to multiple buses'1994 5,325,535'Lock signal extension and interruption apparatus'1994 5,289,584'Memory system with FIFO data input'1994 5,210,847'Noncacheable address random access memory'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2001Patents assigned to COMPAQ COMPUTER CORP (47)· patent assignee history

1993–2021Based in Houston, TX, US· patent location history

1995–2001Based in Tomball, TX, US· patent location history

1999–2000Patents assigned to ADVANCED MICRO DEVICES INC (4)· patent assignee history

2015Patents assigned to HEWLETT PACKARD DEVELOPMENT CO (1)· patent assignee history

2021Patents assigned to HEWLETT PACKARD ENTPR DEV LP (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
COMPAQ COMPUTER CORP	47	1993–2001
ADVANCED MICRO DEVICES INC	4	1999–2000
HEWLETT PACKARD DEVELOPMENT CO	1	2015
HEWLETT PACKARD ENTPR DEV LP	1	2021

Locations

Location	Patents	Span
Tomball, Texas, US	39	1995–2001
Houston, Texas, US	10	1993–2021