Inventor

David K. Cassetti

Inventor

Tempe, AZ, US

Overview

18→

Patents

1996–2020

Patent span

Physics

Primary field (CPC G)

Patents· 18 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing62%

G01RMeasuring electric variables14%

H03MCoding10%

H04LTransmission of digital information, e.g. telegraphic communication10%

H03FAmplifiers5%

PatentTitleYear

10,680,643Compression scheme with control of search agent activity2020 10,224,957Hash-based data matching enhanced with backward matching for data compression2019 9,830,189Multi-threaded queuing system for pattern matching2017 9,223,618'Multi-threaded queuing system for pattern matching'2015 8,705,654'Measuring phase shift in a radio frequency power amplifier'2014 8,370,274'Apparatuses and methods for deterministic pattern matching'2013 7,194,766'Method and system for high-speed processing IPSec security protocol packets'2007 6,385,749'Method and arrangement for controlling multiple test access port control modules'2002 6,334,198'Method and arrangement for controlling multiply-activated test access port control modules'2001 6,311,302'Method and arrangement for hierarchical control of multiple test access port control modules'2001 5,842,012'Efficient soft reset in a personal computer'1998 5,815,675'Method and apparatus for direct access to main memory by an I/O bus'1998 5,793,992'Method and apparatus for arbitrating access to main memory of a computer system'1998 5,794,072'Timing method and apparatus for interleaving PIO and DMA data transfers'1998 5,781,802'First-in-first-out (FIFO) controller for buffering data between systems which are asynchronous and free of false flags and internal metastability'1998 5,752,262'System and method for enabling and disabling writeback cache'1998 5,696,938'Computer system permitting mulitple write buffer read-arounds and method therefor'1997 5,535,360'Digital computer system having an improved direct-mapped cache controller (with flag modification) for a CPU with address pipelining and method therefor'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–1998Patents assigned to VLSI TECHNOLOGY INC (7)· patent assignee history

1996–2020Based in Tempe, AZ, US· patent location history

2001–2002Patents assigned to KONINKL PHILIPS ELECTRONICS NV (2)· patent assignee history

2013–2020Patents assigned to INTEL CORP (5)· patent assignee history

2013–2015Patents assigned to CASSETTI DAVID K (2)· patent assignee history

2013–2015Patents assigned to CLARK CHRISTOPHER F (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
VLSI TECHNOLOGY INC	7	1996–1998
INTEL CORP	5	2013–2020
CASSETTI DAVID Kself	2	2013–2015
CLARK CHRISTOPHER F	2	2013–2015
KONINKL PHILIPS ELECTRONICS NV	2	2001–2002

Locations

Location	Patents	Span
Tempe, AZ, US	18	1996–2020