Inventor

Reid A. Wistort

Inventor

Westford, VT, US

Overview

21→

Patents

1997–2016

Patent span

Physics

Primary field (CPC G)

Patents· 21 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores75%

G01RMeasuring electric variables8%

H03KPulse technique8%

H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses8%

PatentTitleYear

9,384,835'Content addressable memory early-predict late-correct single ended sensing'2016 8,437,201'Word-line level shift circuit'2013 8,233,302'Content addressable memory with concurrent read and search/compare operations at the same memory cell'2012 8,218,378'Word-line level shift circuit'2012 7,924,588'Content addressable memory with concurrent two-dimensional search capability in both row and column directions'2011 7,688,611'CAM asynchronous search-line switching'2010 7,515,449'CAM asynchronous search-line switching'2009 7,117,400'Memory device with data line steering and bitline redundancy'2006 7,049,873'System and method for implementing a micro-stepping delay chain for a delay locked loop'2006 6,998,897'System and method for implementing a micro-stepping delay chain for a delay locked loop'2006 6,791,855'Redundant array architecture for word replacement in CAM'2004 6,728,123'Redundant array architecture for word replacement in CAM'2004 6,697,277'Content addressable memory (CAM) having a match line circuit with selectively adjustable pull-up impedances'2004 6,618,279'Method and apparatus for adjusting control circuit pull-up margin for content addressable memory (CAM)'2003 6,396,336'Sleep mode VDD detune for power reduction'2002 6,373,738'Low power CAM match line circuit'2002 6,356,981'Method and apparatus for preserving data coherency in a double data rate SRAM'2002 6,333,671'Sleep mode VDD detune for power reduction'2001 6,201,750'Scannable fuse latches'2001 5,918,003'Enhanced built-in self-test circuit and method'1999 5,638,315'Content addressable memory for a data processing system'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2013Patents assigned to IBM (20)· patent assignee history

1997–2016Based in Westford, VT, US· patent location history

2012–2016Patents assigned to ARSOVSKI IGOR (4)· patent assignee history

2012–2016Patents assigned to WISTORT REID A (4)· patent assignee history

2012–2013Patents assigned to DEMING MATTHEW W (2)· patent assignee history

2012–2013Patents assigned to HILL DARRYL R (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	20	1997–2013
ARSOVSKI IGOR	4	2012–2016
WISTORT REID Aself	4	2012–2016
DEMING MATTHEW W	2	2012–2013
HILL DARRYL R	2	2012–2013

Locations

Location	Patents	Span
Westford, VT, US	21	1997–2016