Inventor
Masaki Tsukude
Inventor
Hyogo, JP
Overview
Patents· 116 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores64%
H10DInorganic electric semiconductor devices10%
H03KPulse technique9%
H10BElectronic memory devices4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
G05FSystems for regulating electric or magnetic variables4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
G06FElectric digital data processing1%
G01KMeasuring temperature1%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems1%
PatentTitleYear
10,515,672Semiconductor memory device and test method therefor201910,170,161Semiconductor memory device and test method therefor20199,805,821'Semiconductor memory device and test method therefor'20178,061,895'Semiconductor device'20117,983,103'Semiconductor memory device suitable for mounting on portable terminal'2011RE041245'Semiconductor memory device'20107,693,004'Semiconductor memory device'20107,447,098'Semiconductor memory device having complete hidden refresh function'20087,397,298'Semiconductor device having internal power supply voltage generation circuit'20087,301,843'Semiconductor memory device having complete hidden refresh function'20077,145,832'Fully-hidden refresh dynamic random access memory'20067,111,112'Semiconductor memory device having control circuit'20067,061,828'Fully-hidden refresh dynamic random access memory'20066,956,758'Fully-hidden refresh dynamic random access memory'20056,891,770'Fully hidden refresh dynamic random access memory'20056,882,586'Semiconductor memory device equipped with control circuit for controlling memory cell array in non-normal operation mode'20056,859,403'Semiconductor memory device capable of overcoming refresh disturb'20056,859,415'Fully-hidden refresh dynamic random access memory'20056,813,211'Fully hidden refresh dynamic random access memory'20046,798,236'Output buffer circuit with power supply voltages different from a power supply voltage applied to an internal circuit'20046,795,943'Semiconductor device with test mode'20046,744,679'Semiconductor memory device'20046,737,906'Semiconductor integrated circuit device including a negative power supply circuit'20046,721,225'Semiconductor memory device with activation of a burst refresh when a long cycle is detected'20046,717,878'Semiconductor device'20046,714,047'Semiconductor integrated circuit'20046,707,735'Semiconductor memory device'20046,697,910'Semiconductor memory device having refresh circuit'20046,693,838'Semiconductor memory device equipped with refresh timing signal generator'20046,643,208'Semiconductor integrated circuit device having hierarchical power source arrangement'20036,628,559'Semiconductor memory device having refreshing function'20036,590,823'Refresh-circuit-containing semiconductor memory device'20036,584,013'Semiconductor memory device having increased memory capacity while reducing mounting area and stand-by current'20036,577,553'Semiconductor memory device'20036,556,485'Output buffer capable of adjusting current drivability and semiconductor integrated circuit device having the same'20036,525,984'Semiconductor integrated circuit device having hierarchical power source arrangement'20036,501,693'Semiconductor memory device allowing easy characteristics evaluation'20026,493,279'Semiconductor device capable of simple measurement of oscillation frequency'20026,456,129'Internal clock signal generator'20026,434,065'Semiconductor memory device of low power consumption'20026,414,883'Semiconductor memory device'20026,404,056'Semiconductor integrated circuit'20026,341,098'Semiconductor integrated circuit device having hierarchical power source arrangement'20026,331,958'Semiconductor memory device having data parallel/serial conversion function and capable of efficiently performing operational test'20016,272,055'Semiconductor memory device'20016,246,625'Semiconductor integrated circuit device having hierarchical power source arrangement'20016,232,793'Switched backgate bias for FET'20016,205,067'Semiconductor memory device having burn-in mode operation stably accelerated'20016,194,776'Semiconductor circuit device having triple-well structure in semiconductor substrate, method of fabricating the same, and mask device for fabrication of the same'20016,191,461'Semiconductor device including output circuit improved in electrostatic damage resistance'20016,150,728'Semiconductor memory device having a pad arrangement with reduced occupying area'20006,134,171'Semiconductor integrated circuit device having hierarchical power source arrangement'20006,097,180'Voltage supply circuit and semiconductor device including such circuit'20006,075,732'Semiconductor memory device with redundancy circuit'20006,038,183'Semiconductor memory device having burn-in mode operation stably accelerated'20006,011,428'Voltage supply circuit and semiconductor device including such circuit'20006,004,834'Method of manufacturing semiconductor device having a fuse'19995,987,619'Input signal phase compensation circuit capable of reliably obtaining external data'19995,982,678'Semiconductor memory device with redundancy circuit'19995,982,698'Multi-bank system semiconductor memory device capable of operating at high speed'19995,969,420'Semiconductor device comprising a plurality of interconnection patterns'19995,966,340'Semiconductor memory device having hierarchical word line structure'19995,959,927'Semiconductor integrated circuit device having hierarchical power source arrangement'19995,949,731'Semiconductor memory device having burn-in mode operation stably accelerated'19995,943,273'Semiconductor memory device'19995,917,765'Semiconductor memory device capable of burn in mode operation'19995,910,927'Memory device and sense amplifier control device'19995,909,046'Semiconductor integrated circuit device having stable input protection circuit'19995,896,328'Semiconductor memory device allowing writing of desired data to a storage node of a defective memory cell'19995,894,448'Semiconductor memory device having hierarchy control circuit architecture of master/local control circuits permitting high speed accessing'19995,894,440'Semiconductor memory device and data transferring structure and method therein'1999RE036089'Column selecting circuit in semiconductor memory device'1999RE036027'Random access memory of a CSL system with a bit line pair and an I/O line pair independently set to different precharge voltages'19995,856,951'Semiconductor memory device with an improved hierarchical power supply line configuration'19995,854,561'Switched substrate bias for MOS DRAM circuits'19985,848,012'Semiconductor memory device having hierarchical bit line structure employing improved bit line precharging system'19985,844,295'Semiconductor device having a fuse and an improved moisture resistance'19985,838,627'Arrangement of power supply and data input/output pads in semiconductor memory device'19985,831,924'Synchronous semiconductor memory device having a plurality of banks distributed in a plurality of memory arrays'19985,831,921'Semiconductor memory device having signal generating circuitry for sequentially refreshing memory cells in each memory cell block in a self-refresh mode'19985,825,705'Semiconductor memory device having self-refreshing function'19985,815,428'Semiconductor memory device having hierarchical bit line structure'19985,812,490'Synchronous dynamic semiconductor memory device capable of restricting delay of data output timing'19985,757,175'Constant current generating circuit'19985,726,946'Semiconductor integrated circuit device having hierarchical power source arrangement'19985,703,522'Switched substrate bias for MOS-DRAM circuits'19975,696,727'Semiconductor memory device provided with sense amplifier capable of high speed operation with low power consumption'19975,694,364'Semiconductor integrated circuit device having a test mode for reliability evaluation'19975,687,123'Semiconductor memory device'19975,682,343'Hierarchical bit line arrangement in a semiconductor memory'19975,666,315'Semiconductor memory device having a redundancy function suppressible of leakage current from a defective memory cell'19975,659,517'Semiconductor memory device with an improved hierarchical power supply line configuration'19975,652,726'Semiconductor memory device having hierarchical bit line structure employing improved bit line precharging system'19975,652,725'Semiconductor memory device having a redundant row and a redundant column which can be accessed prior to substitution'19975,646,900'Sense amplifier including MOS transistors having threshold voltages controlled dynamically in a semiconductor memory device'19975,633,831'Semiconductor memory device having self-refreshing function'19975,610,533'Switched substrate bias for logic circuits'19975,604,710'Arrangement of power supply and data input/output pads in semiconductor memory device'19975,587,959'Semiconductor memory device'19965,568,440'Semiconductor memory device having self-refreshing function'19965,504,713'Semiconductor memory device with redundancy circuit'19965,408,140'Substrate potential generating circuit generating substrate potential of lower level and semiconductor device including the same'19955,400,290'Semiconductor device allowing accurate characteristics test'19955,321,657'Random access memory of a CSL system with a bit line pair and an I/O line pair independently set to different precharge voltages'19945,315,548'Column selecting circuit in semiconductor memory device'19945,289,417'Semiconductor memory device with redundancy circuit'19945,267,214'Shared-sense amplifier control signal generating circuit in dynamic type semiconductor memory device and operating method therefor'19935,249,155'Semiconductor device incorporating internal voltage down converting circuit'19935,185,744'Semiconductor memory device with test circuit'19935,184,327'Semiconductor memory device having on-chip test circuit and method for testing the same'19935,136,543'Data descrambling in semiconductor memory device'19925,088,064'Dynamic semiconductor memory device of a twisted bit line system having improved reliability of readout'19925,088,063'Semiconductor memory device having on-chip test circuit'19925,060,230'On chip semiconductor memory arbitrary pattern, parallel test apparatus and method'19915,022,007'Test signal generator for semiconductor integrated circuit memory and testing method thereof'19914,977,542'Dynamic semiconductor memory device of a twisted bit line system having improved reliability of readout'1990Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1990–2004Patents assigned to MITSUBISHI ELECTRIC CORP (88)· patent assignee history
1990–2011Based in Hyogo, JP· patent location history
1996–2001Based in Itami, JP· patent location history
1997Based in Hygo, JP· patent location history
1999–2019Based in Tokyo, JP· patent location history
2004–2010Patents assigned to RENESAS TECH CORP (23)· patent assignee history
2011–2019Patents assigned to RENESAS ELECTRONICS CORP (5)· patent assignee history
2011Patents assigned to TSUKUDE MASAKI (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MITSUBISHI ELECTRIC CORP | 88 | 1990–2004 |
| RENESAS TECH CORP | 23 | 2004–2010 |
| RENESAS ELECTRONICS CORP | 5 | 2011–2019 |
| TSUKUDE MASAKIself | 1 | 2011 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hyogo, JP | 89 | 1990–2011 |
| Tokyo, JP | 20 | 1999–2019 |
| Itami, JP | 6 | 1996–2001 |
| Hygo, JP | 1 | 1997 |