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Inventor

Hidetoshi Iwai

Inventor
Ohme, JP

Overview

36→
Patents
1990–2008
Patent span
Physics
Primary field (CPC G)

Patents· 36 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores35%
H10BElectronic memory devices21%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
H10DInorganic electric semiconductor devices8%
G06FElectric digital data processing6%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices5%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
B65DContainers for storage or transport of articles or materials, e.g. bags, barrels, bottles, boxes, cans, cartons, crates, drums, jars, tanks, hoppers, forwarding containers3%
PatentTitleYear
7,464,315'Semiconductor memory device'20087,318,183'Data storing method of dynamic RAM and semiconductor memory device'20087,051,260'Data storing method of dynamic RAM and semiconductor memory device'20066,906,971'Semiconductor integrated circuit device'20056,791,132'Memory semiconductor device with reduced sense amplifier area'20046,697,992'Data storing method of dynamic RAM and semiconductor memory device'20046,680,501'Semiconductor device'20046,078,084'Semiconductor integrated circuit device'20005,910,010'Semiconductor integrated circuit device, and process and apparatus for manufacturing the same'19995,805,513'Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor'19985,736,277'Method of making mask pattern data and process for manufacturing the mask'19985,689,465'Semiconductor memory device and defective memory cell correction circuit'19975,654,577'Semiconductor integrated circuit device'19975,629,898'Dynamic memory device, a memory module, and a method of refreshing a dynamic memory device'19975,610,089'Method of fabrication of semiconductor integrated circuit device'19975,594,279'Semiconductor device having shield wiring for noise suppression'19975,565,285'Method of making mask pattern data and process for manufacturing the mask'19965,550,394'Semiconductor memory device and defective memory cell correction circuit'19965,534,723'Semiconductor integrated circuit device having output and internal circuit MISFETS'19965,498,897'Transistor layout for semiconductor integrated circuit'19965,485,425'Semiconductor memory device having redundant column and operation method thereof'19965,483,490'Semiconductor integrated device and wiring correction arrangement therefor'19965,458,998'Method of making mask pattern data and process for manufacturing the mask'19955,436,484'Semiconductor integrated circuit device having input protective elements and internal circuits'19955,436,483'Semiconductor integrated circuit device having a first MISFET of an output buffer circuit and a second MISFET of an internal circuit'19955,426,613'Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor'19955,410,507'Special mode control method for dynamic random access memory'19955,359,561'Semiconductor memory device'19945,289,416'Semiconductor integrated device and wiring correction arrangement therefor'19945,287,000'Resin-encapsulated semiconductor memory device useful for single in-line packages'19945,276,346'Semiconductor integrated circuit device having protective/output elements and internal circuits'19945,217,917'Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor'19935,208,782'Semiconductor integrated circuit device having a plurality of memory blocks and a lead on chip (LOC) arrangement'19935,151,772'Semiconductor integrated circuit device'19925,047,983'Semiconductor storage device with redundancy arrangement'19914,934,820'Semiconductor device'1990

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1990–2006Patents assigned to HITACHI LTD (33)· patent assignee history
1990–1998Patents assigned to HITACHI VLSI ENG (7)· patent assignee history
1990–2005Based in Ohme, JP· patent location history
1996–1997Patents assigned to TEXAS INSTRUMENTS INC (5)· patent assignee history
1996–1999Based in Ome, JP· patent location history
1996–1997Based in Oume, JP· patent location history
1999Patents assigned to HITACHI HOKKAI SEMICONDUCTOR (1)· patent assignee history
2004–2008Based in Fussa, JP· patent location history
2008Patents assigned to ELPIDA MEMORY INC (2)· patent assignee history
2008Based in Tokyo, JP· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
HITACHI LTD331990–2006
HITACHI VLSI ENG71990–1998
TEXAS INSTRUMENTS INC51996–1997
ELPIDA MEMORY INC22008
HITACHI HOKKAI SEMICONDUCTOR11999
Locations
LocationPatentsSpan
Ohme, JP231990–2005
Fussa, JP52004–2008
Ome, JP31996–1999
Oume, JP21996–1997
Tokyo, JP12008