LexDanaLexDanabeta
Inventor

Jeff J. Xu

Inventor
Jhubei City, TW

Overview

55→
Patents
2007–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 55 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices40%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1027%
H01LSemiconductor devices21%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
H10BElectronic memory devices1%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
PatentTitleYear
10,818,661Fin-like field effect transistor (FinFET) device and method of manufacturing same202010,693,003Integrated circuit transistor structure with high germanium concentration SiGe stressor202010,522,544Techniques providing metal gate devices with multiple barrier layers201910,510,887Method for fabricating a strained structure and structure formed201910,468,408Fin-like field effect transistor (FinFET) device and method of manufacturing same201910,312,236Techniques providing metal gate devices with multiple barrier layers201910,090,300Fin-like field effect transistor (FinFET) device and method of manufacturing same20189,922,827'Method of forming a semiconductor structure'20189,911,735'Fin-like field effect transistor (FinFET) device and method of manufacturing same'20189,831,243Techniques providing metal gate devices with multiple barrier layers20179,660,082'Integrated circuit transistor structure with high germanium concentration SiGe stressor'20179,647,118'Device having EPI film in substrate trench'20179,564,529'Method for fabricating a strained structure and structure formed'20179,425,286'Source/drain stressor having enhanced carrier mobility and method for manufacturing same'20169,356,109'Metal gate transistor and integrated circuits'20169,245,970'Semiconductor structure having interfacial layer and high-k dielectric layer'20169,202,915'Method of forming epi film in substrate trench'20159,190,417'Fin-like field effect transistor (FinFET) device and method of manufacturing same'20159,166,022'Fin-like field effect transistor (FinFET) device and method of manufacturing same'20159,147,594'Method for fabricating a strained structure'20159,142,643'Method for forming epitaxial feature'20159,105,624'Techniques providing metal gate devices with multiple barrier layers'20159,040,393'Method of forming semiconductor structure'20159,006,056'Method for reducing interfacial layer thickness for high-k and metal gate stack'20158,999,794'Self-aligned source and drain structures and method of manufacturing same'20158,895,426'Metal gate transistor, integrated circuits, systems, and fabrication methods thereof'20148,847,333'Techniques providing metal gate devices with multiple barrier layers'20148,704,280'Semiconductor device with strained channels induced by high-k capping metal layers'20148,648,400'FinFET semiconductor device with germanium (GE) fins'20148,629,426'Source/drain stressor having enhanced carrier mobility manufacturing same'20148,623,728'Method for forming high germanium concentration SiGe stressor'20148,597,995'Metal gate device with low temperature oxygen scavenging'20138,524,587'Non-uniformity reduction in semiconductor planarization'20138,501,570'Method of manufacturing source/drain structures'20138,497,528'Method for fabricating a strained structure'20138,497,177'Method of making a FinFET device'20138,470,659'Method for reducing interfacial layer thickness for high-k and metal gate stack'20138,415,718'Method of forming epi film in substrate trench'20138,367,498'Fin-like field effect transistor (FinFET) device and method of manufacturing same'20138,367,534'Non-uniformity reduction in semiconductor planarization'20138,334,570'Metal gate stress film for mobility enhancement in FinFET device'20128,304,841'Metal gate transistor, integrated circuits, systems, and fabrication methods thereof'20128,268,683'Method for reducing interfacial layer thickness for high-K and metal gate stack'20128,241,823'Method of fabrication of a semiconductor device having reduced pitch'20128,124,537'Method for etching integrated circuit structure'20128,106,469'Methods and apparatus of fluorine passivation'20128,053,299'Method of fabrication of a FinFET element'20118,039,179'Integrated circuit layout design'20117,989,355'Method of pitch halving'20117,939,353'Methods of forming integrated circuits'20117,915,112'Metal gate stress film for mobility enhancement in FinFET device'20117,910,453'Storage nitride encapsulation for non-planar sonos NAND flash charge retention'20117,862,962'Integrated circuit layout design'20117,531,102'Simultaneous selective polymer deposition and etch pitch doubling for sub 50nm line/space patterning'20097,235,478'Polymer spacer formation'2007

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2007–2009Based in San Jose, CA, US· patent location history
2011–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (39)· patent assignee history
2011–2020Based in Jhubei City, TW· patent location history
2012–2015Patents assigned to XU JEFF J (22)· patent assignee history
2012–2015Patents assigned to WANN CLEMENT HSINGJEN (4)· patent assignee history
2013–2015Patents assigned to CHANG CHIH-HAO (4)· patent assignee history
2015Based in Hsinchu, TW· patent location history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (14)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TAIWAN SEMICONDUCTOR MFG392011–2016
XU JEFF Jself222012–2015
TAIWAN SEMICONDUCTOR MFG CO LTD142016–2020
CHANG CHIH-HAO42013–2015
WANN CLEMENT HSINGJEN42012–2015
Locations
LocationPatentsSpan
Jhubei City, TW522011–2020
San Jose, California, US22007–2009
Hsinchu, TW12015