Inventor
John P. Dubuque
Inventor
Jericho, VT, US
Overview
Patents· 26 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing93%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses4%
Y02PClimate change mitigation technologies in the production or processing of goods4%
PatentTitleYear
10,970,448Partial parameters and projection thereof included within statistical timing analysis202110,489,540Integrating manufacturing feedback into integrated circuit structure design201910,394,982Partial parameters and projection thereof included within statistical timing analysis20199,858,368'Integrating manufacturing feedback into integrated circuit structure design'20189,519,747'Dynamic and adaptive timing sensitivity during static timing analysis using look-up table'20169,378,328'Modeling multi-patterning variability with statistical timing'20169,348,962'Hierarchical design of integrated circuits with multi-patterning requirements'20169,171,124'Parasitic extraction in an integrated circuit with multi-patterning requirements'20158,949,765'Modeling multi-patterning variability with statistical timing'20158,850,378'Hierarchical design of integrated circuits with multi-patterning requirements'20148,839,167'Reducing runtime and memory requirements of static timing analysis'20148,806,402'Modeling multi-patterning variability with statistical timing'20148,769,452'Parasitic extraction in an integrated circuit with multi-patterning requirements'20148,768,679'System and method for efficient modeling of NPskew effects on static timing tests'20148,656,207'Method for modeling variation in a feedback loop of a phase-locked loop'20148,560,989'Statistical clock cycle computation'20138,468,483'Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence'20138,413,095'Statistical single library including on chip variation for rapid timing and power analysis'20138,141,012'Timing closure on multiple selective corners in a single statistical timing run'20128,056,035'Method and system for analyzing cross-talk coupling noise events in block-based statistical static timing'20117,886,246'Methods for identifying failing timing requirements in a digital design'20117,844,932'Method to identify timing violations outside of manufacturing specification limits'20107,797,657'Parameter ordering for multi-corner static timing analysis'20107,784,003'Estimation of process variation impact of slack in multi-corner path-based static timing analysis'20107,681,157'Variable threshold system and method for multi-corner static timing analysis'20107,555,740'Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009–2021Patents assigned to IBM (25)· patent assignee history
2009–2021Based in Jericho, VT, US· patent location history
2012–2018Patents assigned to DUBUQUE JOHN P (7)· patent assignee history
2012–2018Patents assigned to FOREMAN ERIC A (7)· patent assignee history
2012–2018Patents assigned to HABITZ PETER A (7)· patent assignee history
2012–2018Patents assigned to HEMMETT JEFFREY G (6)· patent assignee history
2012Based in Essex Junction, VT, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 25 | 2009–2021 |
| DUBUQUE JOHN Pself | 7 | 2012–2018 |
| FOREMAN ERIC A | 7 | 2012–2018 |
| HABITZ PETER A | 7 | 2012–2018 |
| HEMMETT JEFFREY G | 6 | 2012–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Jericho, VT, US | 25 | 2009–2021 |
| Essex Junction, VT, US | 1 | 2012 |